From 7659ca1a3e22aa298022b1ecb21bf3650a01e814 Mon Sep 17 00:00:00 2001 From: Suraj Jitindar Singh Date: Fri, 10 Feb 2017 16:25:52 +1100 Subject: target/ppc: Fix LPCR DPFD mask define The DPFD field in the LPCR is 3 bits wide. This has always been defined as 0x3 << shift which indicates a 2 bit field, which is incorrect. Correct this. Signed-off-by: Suraj Jitindar Singh Signed-off-by: David Gibson --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bc2a2ce..bb96dd5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -381,7 +381,7 @@ struct ppc_slb_t { #define LPCR_ISL (1ull << (63 - 2)) #define LPCR_KBV (1ull << (63 - 3)) #define LPCR_DPFD_SHIFT (63 - 11) -#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT) +#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) #define LPCR_VRMASD_SHIFT (63 - 16) #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) #define LPCR_RMLS_SHIFT (63 - 37) -- cgit v1.1