From 6d9650191ae301dc545dd9fd0727c57ec935503e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 6 May 2022 13:02:40 -0500 Subject: target/arm: Enable FEAT_DGH for -cpu max This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 1 + 2 files changed, 2 insertions(+) (limited to 'target') diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 40f77de..f551210 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -738,6 +738,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 = t; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5a02e07..6a27234 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1427,6 +1427,7 @@ static void handle_hint(DisasContext *s, uint32_t insn, break; case 0b00100: /* SEV */ case 0b00101: /* SEVL */ + case 0b00110: /* DGH */ /* we treat all as NOP at least for now */ break; case 0b00111: /* XPACLRI */ -- cgit v1.1