From e69ba2b489d9cc6e976a29a58726d45361d85b9d Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 19 Mar 2018 17:05:05 +1100 Subject: target/ppc: Initialize lazy_tlb_flush correctly ppc_tr_init_disas_context() correctly sets lazy_tlb_flush to true on certain CPU models. However, it leaves it uninitialized, instead of setting it to false on all others. It wasn't caught before now because we didn't have examples in the tests that exercised this path. However it can now be caught using clang's undefined behaviour sanitizer and the sam460ex board. Suggested-by: Peter Maydell Signed-off-by: David Gibson Reviewed-by: Thomas Huth Reviewed-by: Greg Kurz --- target/ppc/translate.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'target') diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 218665b..3457d29 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7237,10 +7237,9 @@ static int ppc_tr_init_disas_context(DisasContextBase *dcbase, ctx->sf_mode = msr_is_64bit(env, env->msr); ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); #endif - if (env->mmu_model == POWERPC_MMU_32B || - env->mmu_model == POWERPC_MMU_601 || - (env->mmu_model & POWERPC_MMU_64B)) - ctx->lazy_tlb_flush = true; + ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B + || env->mmu_model == POWERPC_MMU_601 + || (env->mmu_model & POWERPC_MMU_64B); ctx->fpu_enabled = !!msr_fp; if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) -- cgit v1.1 From efb7db250adad82c4bb302f0a80e4ae0c641f0d6 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Tue, 20 Mar 2018 13:01:18 +1100 Subject: target/ppc: Fix backwards migration of msr_mask MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 21b786f "PowerPC: Add TS bits into msr_mask" added the transaction states to msr_mask for recent POWER CPUs to allow correct migration of machines that are in certain interim transactional memory states. This was correct, but unfortunately breaks backwards of pseries-2.7 and earlier machine types which (stupidly) transferred the msr_mask in the migration stream and failed if it wasn't equal on each end. This works around the problem by masking out the new MSR bits in the compatibility code to send the msr_mask on old machine types. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Tested-by: Greg Kurz Tested-by: Lukáš Doktor --- target/ppc/machine.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/ppc/machine.c b/target/ppc/machine.c index e475206..0634cdb 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -190,7 +190,15 @@ static int cpu_pre_save(void *opaque) /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ if (cpu->pre_2_8_migration) { - cpu->mig_msr_mask = env->msr_mask; + /* Mask out bits that got added to msr_mask since the versions + * which stupidly included it in the migration stream. */ + target_ulong metamask = 0 +#if defined(TARGET_PPC64) + | (1ULL << MSR_TS0) + | (1ULL << MSR_TS1) +#endif + ; + cpu->mig_msr_mask = env->msr_mask & ~metamask; cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; cpu->mig_nb_BATs = env->nb_BATs; -- cgit v1.1