From 3a4e56015b897a5502ab6a691cd4e20700e779c1 Mon Sep 17 00:00:00 2001 From: Michael Tokarev Date: Tue, 14 Nov 2023 19:11:33 +0300 Subject: target/riscv/cpu.h: spelling fix: separatly Fixes: 40336d5b1d4c "target/riscv: Add HS-mode virtual interrupt and IRQ filtering support." Reviewed-by: Thomas Huth Signed-off-by: Michael Tokarev --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf58b0f..d74b361 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -214,13 +214,13 @@ struct CPUArchState { /* * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more - * alias of mie[i] and needs to be maintained separatly. + * alias of mie[i] and needs to be maintained separately. */ uint64_t sie; /* * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more - * alias of sie[i] (mie[i]) and needs to be maintained separatly. + * alias of sie[i] (mie[i]) and needs to be maintained separately. */ uint64_t vsie; -- cgit v1.1