From 2fc1b44dd0e7ea9ad5920352fd04179e4d6836d9 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Tue, 18 Jan 2022 09:45:20 +0800 Subject: target/riscv: rvv-1.0: Allow Zve32f extension to be turned on Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-18-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ef26937..c2b570e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -688,6 +688,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), + DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), -- cgit v1.1