From 080ac33542d7ee042710f05c023fe5e3a70b9ebf Mon Sep 17 00:00:00 2001 From: Dmitry Voronetskiy Date: Sun, 13 Jun 2021 21:08:38 +0300 Subject: target/i386: Tidy hw_breakpoint_remove Since cpu_breakpoint and cpu_watchpoint are in a union, the code should access only one of them. Signed-off-by: Dmitry Voronetskiy Message-Id: <20210613180838.21349-1-davoronetskiy@gmail.com> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/bpt_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/i386/tcg/sysemu/bpt_helper.c b/target/i386/tcg/sysemu/bpt_helper.c index 624f90b..4d96a48 100644 --- a/target/i386/tcg/sysemu/bpt_helper.c +++ b/target/i386/tcg/sysemu/bpt_helper.c @@ -109,9 +109,9 @@ static void hw_breakpoint_remove(CPUX86State *env, int index) case DR7_TYPE_DATA_WR: case DR7_TYPE_DATA_RW: - if (env->cpu_breakpoint[index]) { + if (env->cpu_watchpoint[index]) { cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]); - env->cpu_breakpoint[index] = NULL; + env->cpu_watchpoint[index] = NULL; } break; -- cgit v1.1 From 505910a6e2d5ca374cbbed874251952d113c7919 Mon Sep 17 00:00:00 2001 From: Ziqiao Kong Date: Sun, 30 May 2021 23:01:12 +0800 Subject: target/i386: Trivial code motion and code style fix A new pair of braces has to be added to declare variables in the case block. The code style is also fixed according to the transalte.c itself during the code motion. Signed-off-by: Ziqiao Kong Message-Id: <20210530150112.74411-1-ziqiaokong@gmail.com> Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 881 ++++++++++++++++++++++---------------------- 1 file changed, 446 insertions(+), 435 deletions(-) (limited to 'target') diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 3814ce2..a43e577 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -5919,503 +5919,514 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /************************/ /* floats */ case 0xd8 ... 0xdf: - if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { - /* if CR0.EM or CR0.TS are set, generate an FPU exception */ - /* XXX: what to do if illegal op ? */ - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); - break; - } - modrm = x86_ldub_code(env, s); - mod = (modrm >> 6) & 3; - rm = modrm & 7; - op = ((b & 7) << 3) | ((modrm >> 3) & 7); - if (mod != 3) { - /* memory op */ - gen_lea_modrm(env, s, modrm); - switch(op) { - case 0x00 ... 0x07: /* fxxxs */ - case 0x10 ... 0x17: /* fixxxl */ - case 0x20 ... 0x27: /* fxxxl */ - case 0x30 ... 0x37: /* fixxx */ - { - int op1; - op1 = op & 7; + { + if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { + /* if CR0.EM or CR0.TS are set, generate an FPU exception */ + /* XXX: what to do if illegal op ? */ + gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); + break; + } + modrm = x86_ldub_code(env, s); + mod = (modrm >> 6) & 3; + rm = modrm & 7; + op = ((b & 7) << 3) | ((modrm >> 3) & 7); + if (mod != 3) { + /* memory op */ + gen_lea_modrm(env, s, modrm); + switch (op) { + case 0x00 ... 0x07: /* fxxxs */ + case 0x10 ... 0x17: /* fixxxl */ + case 0x20 ... 0x27: /* fxxxl */ + case 0x30 ... 0x37: /* fixxx */ + { + int op1; + op1 = op & 7; + + switch (op >> 4) { + case 0: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + gen_helper_flds_FT0(cpu_env, s->tmp2_i32); + break; + case 1: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); + break; + case 2: + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + gen_helper_fldl_FT0(cpu_env, s->tmp1_i64); + break; + case 3: + default: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LESW); + gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); + break; + } - switch(op >> 4) { + gen_helper_fp_arith_ST0_FT0(op1); + if (op1 == 3) { + /* fcomp needs pop */ + gen_helper_fpop(cpu_env); + } + } + break; + case 0x08: /* flds */ + case 0x0a: /* fsts */ + case 0x0b: /* fstps */ + case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ + case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ + case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ + switch (op & 7) { case 0: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - gen_helper_flds_FT0(cpu_env, s->tmp2_i32); + switch (op >> 4) { + case 0: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + gen_helper_flds_ST0(cpu_env, s->tmp2_i32); + break; + case 1: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + break; + case 2: + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + gen_helper_fldl_ST0(cpu_env, s->tmp1_i64); + break; + case 3: + default: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LESW); + gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + break; + } break; case 1: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); - break; - case 2: - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, - s->mem_index, MO_LEQ); - gen_helper_fldl_FT0(cpu_env, s->tmp1_i64); + /* XXX: the corresponding CPUID bit must be tested ! */ + switch (op >> 4) { + case 1: + gen_helper_fisttl_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + break; + case 2: + gen_helper_fisttll_ST0(s->tmp1_i64, cpu_env); + tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + break; + case 3: + default: + gen_helper_fistt_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + break; + } + gen_helper_fpop(cpu_env); break; - case 3: default: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LESW); - gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); + switch (op >> 4) { + case 0: + gen_helper_fsts_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + break; + case 1: + gen_helper_fistl_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + break; + case 2: + gen_helper_fstl_ST0(s->tmp1_i64, cpu_env); + tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + break; + case 3: + default: + gen_helper_fist_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + break; + } + if ((op & 7) == 3) { + gen_helper_fpop(cpu_env); + } break; } + break; + case 0x0c: /* fldenv mem */ + gen_helper_fldenv(cpu_env, s->A0, + tcg_const_i32(dflag - 1)); + break; + case 0x0d: /* fldcw mem */ + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + gen_helper_fldcw(cpu_env, s->tmp2_i32); + break; + case 0x0e: /* fnstenv mem */ + gen_helper_fstenv(cpu_env, s->A0, + tcg_const_i32(dflag - 1)); + break; + case 0x0f: /* fnstcw mem */ + gen_helper_fnstcw(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + break; + case 0x1d: /* fldt mem */ + gen_helper_fldt_ST0(cpu_env, s->A0); + break; + case 0x1f: /* fstpt mem */ + gen_helper_fstt_ST0(cpu_env, s->A0); + gen_helper_fpop(cpu_env); + break; + case 0x2c: /* frstor mem */ + gen_helper_frstor(cpu_env, s->A0, + tcg_const_i32(dflag - 1)); + break; + case 0x2e: /* fnsave mem */ + gen_helper_fsave(cpu_env, s->A0, + tcg_const_i32(dflag - 1)); + break; + case 0x2f: /* fnstsw mem */ + gen_helper_fnstsw(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + break; + case 0x3c: /* fbld */ + gen_helper_fbld_ST0(cpu_env, s->A0); + break; + case 0x3e: /* fbstp */ + gen_helper_fbst_ST0(cpu_env, s->A0); + gen_helper_fpop(cpu_env); + break; + case 0x3d: /* fildll */ + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + gen_helper_fildll_ST0(cpu_env, s->tmp1_i64); + break; + case 0x3f: /* fistpll */ + gen_helper_fistll_ST0(s->tmp1_i64, cpu_env); + tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + gen_helper_fpop(cpu_env); + break; + default: + goto unknown_op; + } + } else { + /* register float ops */ + opreg = rm; - gen_helper_fp_arith_ST0_FT0(op1); - if (op1 == 3) { - /* fcomp needs pop */ - gen_helper_fpop(cpu_env); + switch (op) { + case 0x08: /* fld sti */ + gen_helper_fpush(cpu_env); + gen_helper_fmov_ST0_STN(cpu_env, + tcg_const_i32((opreg + 1) & 7)); + break; + case 0x09: /* fxchg sti */ + case 0x29: /* fxchg4 sti, undocumented op */ + case 0x39: /* fxchg7 sti, undocumented op */ + gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); + break; + case 0x0a: /* grp d9/2 */ + switch (rm) { + case 0: /* fnop */ + /* check exceptions (FreeBSD FPU probe) */ + gen_helper_fwait(cpu_env); + break; + default: + goto unknown_op; } - } - break; - case 0x08: /* flds */ - case 0x0a: /* fsts */ - case 0x0b: /* fstps */ - case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ - case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ - case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ - switch(op & 7) { - case 0: - switch(op >> 4) { - case 0: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - gen_helper_flds_ST0(cpu_env, s->tmp2_i32); + break; + case 0x0c: /* grp d9/4 */ + switch (rm) { + case 0: /* fchs */ + gen_helper_fchs_ST0(cpu_env); break; - case 1: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + case 1: /* fabs */ + gen_helper_fabs_ST0(cpu_env); break; - case 2: - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, - s->mem_index, MO_LEQ); - gen_helper_fldl_ST0(cpu_env, s->tmp1_i64); + case 4: /* ftst */ + gen_helper_fldz_FT0(cpu_env); + gen_helper_fcom_ST0_FT0(cpu_env); break; - case 3: - default: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LESW); - gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + case 5: /* fxam */ + gen_helper_fxam_ST0(cpu_env); break; + default: + goto unknown_op; } break; - case 1: - /* XXX: the corresponding CPUID bit must be tested ! */ - switch(op >> 4) { - case 1: - gen_helper_fisttl_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); + case 0x0d: /* grp d9/5 */ + { + switch (rm) { + case 0: + gen_helper_fpush(cpu_env); + gen_helper_fld1_ST0(cpu_env); + break; + case 1: + gen_helper_fpush(cpu_env); + gen_helper_fldl2t_ST0(cpu_env); + break; + case 2: + gen_helper_fpush(cpu_env); + gen_helper_fldl2e_ST0(cpu_env); + break; + case 3: + gen_helper_fpush(cpu_env); + gen_helper_fldpi_ST0(cpu_env); + break; + case 4: + gen_helper_fpush(cpu_env); + gen_helper_fldlg2_ST0(cpu_env); + break; + case 5: + gen_helper_fpush(cpu_env); + gen_helper_fldln2_ST0(cpu_env); + break; + case 6: + gen_helper_fpush(cpu_env); + gen_helper_fldz_ST0(cpu_env); + break; + default: + goto unknown_op; + } + } + break; + case 0x0e: /* grp d9/6 */ + switch (rm) { + case 0: /* f2xm1 */ + gen_helper_f2xm1(cpu_env); break; - case 2: - gen_helper_fisttll_ST0(s->tmp1_i64, cpu_env); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, - s->mem_index, MO_LEQ); + case 1: /* fyl2x */ + gen_helper_fyl2x(cpu_env); + break; + case 2: /* fptan */ + gen_helper_fptan(cpu_env); + break; + case 3: /* fpatan */ + gen_helper_fpatan(cpu_env); + break; + case 4: /* fxtract */ + gen_helper_fxtract(cpu_env); + break; + case 5: /* fprem1 */ + gen_helper_fprem1(cpu_env); + break; + case 6: /* fdecstp */ + gen_helper_fdecstp(cpu_env); break; - case 3: default: - gen_helper_fistt_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); + case 7: /* fincstp */ + gen_helper_fincstp(cpu_env); break; } - gen_helper_fpop(cpu_env); break; - default: - switch(op >> 4) { - case 0: - gen_helper_fsts_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); + case 0x0f: /* grp d9/7 */ + switch (rm) { + case 0: /* fprem */ + gen_helper_fprem(cpu_env); break; - case 1: - gen_helper_fistl_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); + case 1: /* fyl2xp1 */ + gen_helper_fyl2xp1(cpu_env); break; - case 2: - gen_helper_fstl_ST0(s->tmp1_i64, cpu_env); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, - s->mem_index, MO_LEQ); + case 2: /* fsqrt */ + gen_helper_fsqrt(cpu_env); + break; + case 3: /* fsincos */ + gen_helper_fsincos(cpu_env); + break; + case 5: /* fscale */ + gen_helper_fscale(cpu_env); + break; + case 4: /* frndint */ + gen_helper_frndint(cpu_env); + break; + case 6: /* fsin */ + gen_helper_fsin(cpu_env); break; - case 3: default: - gen_helper_fist_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); + case 7: /* fcos */ + gen_helper_fcos(cpu_env); break; } - if ((op & 7) == 3) - gen_helper_fpop(cpu_env); - break; - } - break; - case 0x0c: /* fldenv mem */ - gen_helper_fldenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); - break; - case 0x0d: /* fldcw mem */ - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); - gen_helper_fldcw(cpu_env, s->tmp2_i32); - break; - case 0x0e: /* fnstenv mem */ - gen_helper_fstenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); - break; - case 0x0f: /* fnstcw mem */ - gen_helper_fnstcw(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); - break; - case 0x1d: /* fldt mem */ - gen_helper_fldt_ST0(cpu_env, s->A0); - break; - case 0x1f: /* fstpt mem */ - gen_helper_fstt_ST0(cpu_env, s->A0); - gen_helper_fpop(cpu_env); - break; - case 0x2c: /* frstor mem */ - gen_helper_frstor(cpu_env, s->A0, tcg_const_i32(dflag - 1)); - break; - case 0x2e: /* fnsave mem */ - gen_helper_fsave(cpu_env, s->A0, tcg_const_i32(dflag - 1)); - break; - case 0x2f: /* fnstsw mem */ - gen_helper_fnstsw(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); - break; - case 0x3c: /* fbld */ - gen_helper_fbld_ST0(cpu_env, s->A0); - break; - case 0x3e: /* fbstp */ - gen_helper_fbst_ST0(cpu_env, s->A0); - gen_helper_fpop(cpu_env); - break; - case 0x3d: /* fildll */ - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ); - gen_helper_fildll_ST0(cpu_env, s->tmp1_i64); - break; - case 0x3f: /* fistpll */ - gen_helper_fistll_ST0(s->tmp1_i64, cpu_env); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ); - gen_helper_fpop(cpu_env); - break; - default: - goto unknown_op; - } - } else { - /* register float ops */ - opreg = rm; - - switch(op) { - case 0x08: /* fld sti */ - gen_helper_fpush(cpu_env); - gen_helper_fmov_ST0_STN(cpu_env, - tcg_const_i32((opreg + 1) & 7)); - break; - case 0x09: /* fxchg sti */ - case 0x29: /* fxchg4 sti, undocumented op */ - case 0x39: /* fxchg7 sti, undocumented op */ - gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); - break; - case 0x0a: /* grp d9/2 */ - switch(rm) { - case 0: /* fnop */ - /* check exceptions (FreeBSD FPU probe) */ - gen_helper_fwait(cpu_env); break; - default: - goto unknown_op; - } - break; - case 0x0c: /* grp d9/4 */ - switch(rm) { - case 0: /* fchs */ - gen_helper_fchs_ST0(cpu_env); - break; - case 1: /* fabs */ - gen_helper_fabs_ST0(cpu_env); + case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ + case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ + case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ + { + int op1; + + op1 = op & 7; + if (op >= 0x20) { + gen_helper_fp_arith_STN_ST0(op1, opreg); + if (op >= 0x30) { + gen_helper_fpop(cpu_env); + } + } else { + gen_helper_fmov_FT0_STN(cpu_env, + tcg_const_i32(opreg)); + gen_helper_fp_arith_ST0_FT0(op1); + } + } break; - case 4: /* ftst */ - gen_helper_fldz_FT0(cpu_env); + case 0x02: /* fcom */ + case 0x22: /* fcom2, undocumented op */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fcom_ST0_FT0(cpu_env); break; - case 5: /* fxam */ - gen_helper_fxam_ST0(cpu_env); + case 0x03: /* fcomp */ + case 0x23: /* fcomp3, undocumented op */ + case 0x32: /* fcomp5, undocumented op */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fcom_ST0_FT0(cpu_env); + gen_helper_fpop(cpu_env); break; - default: - goto unknown_op; - } - break; - case 0x0d: /* grp d9/5 */ - { - switch(rm) { - case 0: - gen_helper_fpush(cpu_env); - gen_helper_fld1_ST0(cpu_env); - break; - case 1: - gen_helper_fpush(cpu_env); - gen_helper_fldl2t_ST0(cpu_env); + case 0x15: /* da/5 */ + switch (rm) { + case 1: /* fucompp */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); + gen_helper_fucom_ST0_FT0(cpu_env); + gen_helper_fpop(cpu_env); + gen_helper_fpop(cpu_env); break; - case 2: - gen_helper_fpush(cpu_env); - gen_helper_fldl2e_ST0(cpu_env); + default: + goto unknown_op; + } + break; + case 0x1c: + switch (rm) { + case 0: /* feni (287 only, just do nop here) */ break; - case 3: - gen_helper_fpush(cpu_env); - gen_helper_fldpi_ST0(cpu_env); + case 1: /* fdisi (287 only, just do nop here) */ break; - case 4: - gen_helper_fpush(cpu_env); - gen_helper_fldlg2_ST0(cpu_env); + case 2: /* fclex */ + gen_helper_fclex(cpu_env); break; - case 5: - gen_helper_fpush(cpu_env); - gen_helper_fldln2_ST0(cpu_env); + case 3: /* fninit */ + gen_helper_fninit(cpu_env); break; - case 6: - gen_helper_fpush(cpu_env); - gen_helper_fldz_ST0(cpu_env); + case 4: /* fsetpm (287 only, just do nop here) */ break; default: goto unknown_op; } - } - break; - case 0x0e: /* grp d9/6 */ - switch(rm) { - case 0: /* f2xm1 */ - gen_helper_f2xm1(cpu_env); - break; - case 1: /* fyl2x */ - gen_helper_fyl2x(cpu_env); - break; - case 2: /* fptan */ - gen_helper_fptan(cpu_env); - break; - case 3: /* fpatan */ - gen_helper_fpatan(cpu_env); - break; - case 4: /* fxtract */ - gen_helper_fxtract(cpu_env); - break; - case 5: /* fprem1 */ - gen_helper_fprem1(cpu_env); - break; - case 6: /* fdecstp */ - gen_helper_fdecstp(cpu_env); - break; - default: - case 7: /* fincstp */ - gen_helper_fincstp(cpu_env); break; - } - break; - case 0x0f: /* grp d9/7 */ - switch(rm) { - case 0: /* fprem */ - gen_helper_fprem(cpu_env); - break; - case 1: /* fyl2xp1 */ - gen_helper_fyl2xp1(cpu_env); - break; - case 2: /* fsqrt */ - gen_helper_fsqrt(cpu_env); + case 0x1d: /* fucomi */ + if (!(s->cpuid_features & CPUID_CMOV)) { + goto illegal_op; + } + gen_update_cc_op(s); + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fucomi_ST0_FT0(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); break; - case 3: /* fsincos */ - gen_helper_fsincos(cpu_env); + case 0x1e: /* fcomi */ + if (!(s->cpuid_features & CPUID_CMOV)) { + goto illegal_op; + } + gen_update_cc_op(s); + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fcomi_ST0_FT0(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); break; - case 5: /* fscale */ - gen_helper_fscale(cpu_env); + case 0x28: /* ffree sti */ + gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); break; - case 4: /* frndint */ - gen_helper_frndint(cpu_env); + case 0x2a: /* fst sti */ + gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); break; - case 6: /* fsin */ - gen_helper_fsin(cpu_env); + case 0x2b: /* fstp sti */ + case 0x0b: /* fstp1 sti, undocumented op */ + case 0x3a: /* fstp8 sti, undocumented op */ + case 0x3b: /* fstp9 sti, undocumented op */ + gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); + gen_helper_fpop(cpu_env); break; - default: - case 7: /* fcos */ - gen_helper_fcos(cpu_env); + case 0x2c: /* fucom st(i) */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fucom_ST0_FT0(cpu_env); break; - } - break; - case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ - case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ - case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ - { - int op1; - - op1 = op & 7; - if (op >= 0x20) { - gen_helper_fp_arith_STN_ST0(op1, opreg); - if (op >= 0x30) - gen_helper_fpop(cpu_env); - } else { - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fp_arith_ST0_FT0(op1); - } - } - break; - case 0x02: /* fcom */ - case 0x22: /* fcom2, undocumented op */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fcom_ST0_FT0(cpu_env); - break; - case 0x03: /* fcomp */ - case 0x23: /* fcomp3, undocumented op */ - case 0x32: /* fcomp5, undocumented op */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fcom_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - break; - case 0x15: /* da/5 */ - switch(rm) { - case 1: /* fucompp */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); + case 0x2d: /* fucomp st(i) */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fucom_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); - gen_helper_fpop(cpu_env); break; - default: - goto unknown_op; - } - break; - case 0x1c: - switch(rm) { - case 0: /* feni (287 only, just do nop here) */ - break; - case 1: /* fdisi (287 only, just do nop here) */ - break; - case 2: /* fclex */ - gen_helper_fclex(cpu_env); + case 0x33: /* de/3 */ + switch (rm) { + case 1: /* fcompp */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); + gen_helper_fcom_ST0_FT0(cpu_env); + gen_helper_fpop(cpu_env); + gen_helper_fpop(cpu_env); + break; + default: + goto unknown_op; + } break; - case 3: /* fninit */ - gen_helper_fninit(cpu_env); + case 0x38: /* ffreep sti, undocumented op */ + gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fpop(cpu_env); break; - case 4: /* fsetpm (287 only, just do nop here) */ + case 0x3c: /* df/4 */ + switch (rm) { + case 0: + gen_helper_fnstsw(s->tmp2_i32, cpu_env); + tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); + gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); + break; + default: + goto unknown_op; + } break; - default: - goto unknown_op; - } - break; - case 0x1d: /* fucomi */ - if (!(s->cpuid_features & CPUID_CMOV)) { - goto illegal_op; - } - gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fucomi_ST0_FT0(cpu_env); - set_cc_op(s, CC_OP_EFLAGS); - break; - case 0x1e: /* fcomi */ - if (!(s->cpuid_features & CPUID_CMOV)) { - goto illegal_op; - } - gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fcomi_ST0_FT0(cpu_env); - set_cc_op(s, CC_OP_EFLAGS); - break; - case 0x28: /* ffree sti */ - gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); - break; - case 0x2a: /* fst sti */ - gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); - break; - case 0x2b: /* fstp sti */ - case 0x0b: /* fstp1 sti, undocumented op */ - case 0x3a: /* fstp8 sti, undocumented op */ - case 0x3b: /* fstp9 sti, undocumented op */ - gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); - gen_helper_fpop(cpu_env); - break; - case 0x2c: /* fucom st(i) */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fucom_ST0_FT0(cpu_env); - break; - case 0x2d: /* fucomp st(i) */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fucom_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - break; - case 0x33: /* de/3 */ - switch(rm) { - case 1: /* fcompp */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); - gen_helper_fcom_ST0_FT0(cpu_env); + case 0x3d: /* fucomip */ + if (!(s->cpuid_features & CPUID_CMOV)) { + goto illegal_op; + } + gen_update_cc_op(s); + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fucomi_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); + break; + case 0x3e: /* fcomip */ + if (!(s->cpuid_features & CPUID_CMOV)) { + goto illegal_op; + } + gen_update_cc_op(s); + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fcomi_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); break; - default: - goto unknown_op; - } - break; - case 0x38: /* ffreep sti, undocumented op */ - gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fpop(cpu_env); - break; - case 0x3c: /* df/4 */ - switch(rm) { - case 0: - gen_helper_fnstsw(s->tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); - gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); + case 0x10 ... 0x13: /* fcmovxx */ + case 0x18 ... 0x1b: + { + int op1; + TCGLabel *l1; + static const uint8_t fcmov_cc[8] = { + (JCC_B << 1), + (JCC_Z << 1), + (JCC_BE << 1), + (JCC_P << 1), + }; + + if (!(s->cpuid_features & CPUID_CMOV)) { + goto illegal_op; + } + op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); + l1 = gen_new_label(); + gen_jcc1_noeob(s, op1, l1); + gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); + gen_set_label(l1); + } break; default: goto unknown_op; } - break; - case 0x3d: /* fucomip */ - if (!(s->cpuid_features & CPUID_CMOV)) { - goto illegal_op; - } - gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fucomi_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - set_cc_op(s, CC_OP_EFLAGS); - break; - case 0x3e: /* fcomip */ - if (!(s->cpuid_features & CPUID_CMOV)) { - goto illegal_op; - } - gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fcomi_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - set_cc_op(s, CC_OP_EFLAGS); - break; - case 0x10 ... 0x13: /* fcmovxx */ - case 0x18 ... 0x1b: - { - int op1; - TCGLabel *l1; - static const uint8_t fcmov_cc[8] = { - (JCC_B << 1), - (JCC_Z << 1), - (JCC_BE << 1), - (JCC_P << 1), - }; - - if (!(s->cpuid_features & CPUID_CMOV)) { - goto illegal_op; - } - op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); - l1 = gen_new_label(); - gen_jcc1_noeob(s, op1, l1); - gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); - gen_set_label(l1); - } - break; - default: - goto unknown_op; } } break; -- cgit v1.1 From bbdda9b74f289328e9ee7be28bb472350dc84028 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 7 Jul 2021 14:45:19 -0700 Subject: target/i386: Split out do_fninit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not call helper_fninit directly from helper_xrstor. Do call the new helper from do_fsave. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) (limited to 'target') diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 74bbe94..beb63be 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -727,7 +727,7 @@ void helper_fwait(CPUX86State *env) } } -void helper_fninit(CPUX86State *env) +static void do_fninit(CPUX86State *env) { env->fpus = 0; env->fpstt = 0; @@ -742,6 +742,11 @@ void helper_fninit(CPUX86State *env) env->fptags[7] = 1; } +void helper_fninit(CPUX86State *env) +{ + do_fninit(env); +} + /* BCD ops */ void helper_fbld_ST0(CPUX86State *env, target_ulong ptr) @@ -2451,18 +2456,7 @@ static void do_fsave(CPUX86State *env, target_ulong ptr, int data32, ptr += 10; } - /* fninit */ - env->fpus = 0; - env->fpstt = 0; - cpu_set_fpuc(env, 0x37f); - env->fptags[0] = 1; - env->fptags[1] = 1; - env->fptags[2] = 1; - env->fptags[3] = 1; - env->fptags[4] = 1; - env->fptags[5] = 1; - env->fptags[6] = 1; - env->fptags[7] = 1; + do_fninit(env); } void helper_fsave(CPUX86State *env, target_ulong ptr, int data32) @@ -2834,7 +2828,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm) if (xstate_bv & XSTATE_FP_MASK) { do_xrstor_fpu(env, ptr, ra); } else { - helper_fninit(env); + do_fninit(env); memset(env->fpregs, 0, sizeof(env->fpregs)); } } -- cgit v1.1 From 84abdd7d271c2df69a9d394be093efd885da7a4c Mon Sep 17 00:00:00 2001 From: Ziqiao Kong Date: Sun, 30 May 2021 23:01:14 +0800 Subject: target/i386: Correct implementation for FCS, FIP, FDS and FDP Update FCS:FIP and FDS:FDP according to the Intel Manual Vol.1 8.1.8. Note that CPUID.(EAX=07H,ECX=0H):EBX[bit 13] is not implemented by design in this patch and will be added along with TCG features flag in a separate patch later. Signed-off-by: Ziqiao Kong Message-Id: <20210530150112.74411-2-ziqiaokong@gmail.com> [rth: Push FDS/FDP handling down into mod != 3 case; free last_addr.] Signed-off-by: Richard Henderson --- target/i386/cpu.h | 2 ++ target/i386/tcg/fpu_helper.c | 20 ++++++++++++-------- target/i386/tcg/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 56 insertions(+), 9 deletions(-) (limited to 'target') diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8f3747d..3dc52de 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1437,6 +1437,8 @@ typedef struct CPUX86State { FPReg fpregs[8]; /* KVM-only so far */ uint16_t fpop; + uint16_t fpcs; + uint16_t fpds; uint64_t fpip; uint64_t fpdp; diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index beb63be..cdd8e9f 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -731,6 +731,10 @@ static void do_fninit(CPUX86State *env) { env->fpus = 0; env->fpstt = 0; + env->fpcs = 0; + env->fpds = 0; + env->fpip = 0; + env->fpdp = 0; cpu_set_fpuc(env, 0x37f); env->fptags[0] = 1; env->fptags[1] = 1; @@ -2378,19 +2382,19 @@ static void do_fstenv(CPUX86State *env, target_ulong ptr, int data32, cpu_stl_data_ra(env, ptr, env->fpuc, retaddr); cpu_stl_data_ra(env, ptr + 4, fpus, retaddr); cpu_stl_data_ra(env, ptr + 8, fptag, retaddr); - cpu_stl_data_ra(env, ptr + 12, 0, retaddr); /* fpip */ - cpu_stl_data_ra(env, ptr + 16, 0, retaddr); /* fpcs */ - cpu_stl_data_ra(env, ptr + 20, 0, retaddr); /* fpoo */ - cpu_stl_data_ra(env, ptr + 24, 0, retaddr); /* fpos */ + cpu_stl_data_ra(env, ptr + 12, env->fpip, retaddr); /* fpip */ + cpu_stl_data_ra(env, ptr + 16, env->fpcs, retaddr); /* fpcs */ + cpu_stl_data_ra(env, ptr + 20, env->fpdp, retaddr); /* fpoo */ + cpu_stl_data_ra(env, ptr + 24, env->fpds, retaddr); /* fpos */ } else { /* 16 bit */ cpu_stw_data_ra(env, ptr, env->fpuc, retaddr); cpu_stw_data_ra(env, ptr + 2, fpus, retaddr); cpu_stw_data_ra(env, ptr + 4, fptag, retaddr); - cpu_stw_data_ra(env, ptr + 6, 0, retaddr); - cpu_stw_data_ra(env, ptr + 8, 0, retaddr); - cpu_stw_data_ra(env, ptr + 10, 0, retaddr); - cpu_stw_data_ra(env, ptr + 12, 0, retaddr); + cpu_stw_data_ra(env, ptr + 6, env->fpip, retaddr); + cpu_stw_data_ra(env, ptr + 8, env->fpcs, retaddr); + cpu_stw_data_ra(env, ptr + 10, env->fpdp, retaddr); + cpu_stw_data_ra(env, ptr + 12, env->fpds, retaddr); } } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a43e577..8520d5a 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -5920,6 +5920,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* floats */ case 0xd8 ... 0xdf: { + bool update_fip = true; + if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { /* if CR0.EM or CR0.TS are set, generate an FPU exception */ /* XXX: what to do if illegal op ? */ @@ -5932,7 +5934,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) op = ((b & 7) << 3) | ((modrm >> 3) & 7); if (mod != 3) { /* memory op */ - gen_lea_modrm(env, s, modrm); + AddressParts a = gen_lea_modrm_0(env, s, modrm); + TCGv ea = gen_lea_modrm_1(s, a); + TCGv last_addr = tcg_temp_new(); + bool update_fdp = true; + + tcg_gen_mov_tl(last_addr, ea); + gen_lea_v_seg(s, s->aflag, ea, a.def_seg, s->override); + switch (op) { case 0x00 ... 0x07: /* fxxxs */ case 0x10 ... 0x17: /* fixxxl */ @@ -6060,20 +6069,24 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x0c: /* fldenv mem */ gen_helper_fldenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); + update_fip = update_fdp = false; break; case 0x0d: /* fldcw mem */ tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); gen_helper_fldcw(cpu_env, s->tmp2_i32); + update_fip = update_fdp = false; break; case 0x0e: /* fnstenv mem */ gen_helper_fstenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); + update_fip = update_fdp = false; break; case 0x0f: /* fnstcw mem */ gen_helper_fnstcw(s->tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); + update_fip = update_fdp = false; break; case 0x1d: /* fldt mem */ gen_helper_fldt_ST0(cpu_env, s->A0); @@ -6085,15 +6098,18 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x2c: /* frstor mem */ gen_helper_frstor(cpu_env, s->A0, tcg_const_i32(dflag - 1)); + update_fip = update_fdp = false; break; case 0x2e: /* fnsave mem */ gen_helper_fsave(cpu_env, s->A0, tcg_const_i32(dflag - 1)); + update_fip = update_fdp = false; break; case 0x2f: /* fnstsw mem */ gen_helper_fnstsw(s->tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); + update_fip = update_fdp = false; break; case 0x3c: /* fbld */ gen_helper_fbld_ST0(cpu_env, s->A0); @@ -6116,6 +6132,19 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) default: goto unknown_op; } + + if (update_fdp) { + int last_seg = s->override >= 0 ? s->override : a.def_seg; + + tcg_gen_ld_i32(s->tmp2_i32, cpu_env, + offsetof(CPUX86State, + segs[last_seg].selector)); + tcg_gen_st16_i32(s->tmp2_i32, cpu_env, + offsetof(CPUX86State, fpds)); + tcg_gen_st_tl(last_addr, cpu_env, + offsetof(CPUX86State, fpdp)); + } + tcg_temp_free(last_addr); } else { /* register float ops */ opreg = rm; @@ -6136,6 +6165,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0: /* fnop */ /* check exceptions (FreeBSD FPU probe) */ gen_helper_fwait(cpu_env); + update_fip = false; break; default: goto unknown_op; @@ -6305,9 +6335,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 2: /* fclex */ gen_helper_fclex(cpu_env); + update_fip = false; break; case 3: /* fninit */ gen_helper_fninit(cpu_env); + update_fip = false; break; case 4: /* fsetpm (287 only, just do nop here) */ break; @@ -6428,6 +6460,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto unknown_op; } } + + if (update_fip) { + tcg_gen_ld_i32(s->tmp2_i32, cpu_env, + offsetof(CPUX86State, segs[R_CS].selector)); + tcg_gen_st16_i32(s->tmp2_i32, cpu_env, + offsetof(CPUX86State, fpcs)); + tcg_gen_st_tl(tcg_constant_tl(pc_start - s->cs_base), + cpu_env, offsetof(CPUX86State, fpip)); + } } break; /************************/ -- cgit v1.1 From 492f85b92adf4e6fbe15b9cd4a36d5e0c3f2c44a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 7 Jul 2021 18:22:19 -0700 Subject: target/alpha: Store set into rx flag A paste-o meant that we wrote back the existing value of the RX flag rather than changing it to TMP. Use tcg_constant_i64 while we're at it. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'target') diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 833d3ba..b439b57 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1084,15 +1084,11 @@ static void gen_msk_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit, static void gen_rx(DisasContext *ctx, int ra, int set) { - TCGv tmp; - if (ra != 31) { ld_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); } - tmp = tcg_const_i64(set); - st_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); - tcg_temp_free(tmp); + st_flag_byte(tcg_constant_i64(set), ENV_FLAG_RX_SHIFT); } static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) -- cgit v1.1 From 3e646c3a3cfb1ce9522c230c2cbbafaf42f0a9c5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 7 Jul 2021 18:46:32 -0700 Subject: target/alpha: Use dest_sink for HW_RET temporary This temp is automatically freed, just like ctx->lit. But we're about to remove ctx->lit, so use sink instead. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target') diff --git a/target/alpha/translate.c b/target/alpha/translate.c index b439b57..64c4865 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2717,7 +2717,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return address from EXC_ADDR. This turns out to be useful for our emulation PALcode, so continue to accept it. */ - ctx->lit = vb = tcg_temp_new(); + vb = dest_sink(ctx); tcg_gen_ld_i64(vb, cpu_env, offsetof(CPUAlphaState, exc_addr)); } else { vb = load_gpr(ctx, rb); -- cgit v1.1 From 212c88c0c78b1b2027b91d0669b92c49d921e91c Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 7 Jul 2021 18:50:46 -0700 Subject: target/alpha: Use tcg_constant_i64 for zero and lit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These constant temps do not need to be freed, and therefore need less bookkeeping from tcg producers. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) (limited to 'target') diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 64c4865..58c0e08 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -66,8 +66,6 @@ struct DisasContext { /* Temporaries for $31 and $f31 as source and destination. */ TCGv zero; TCGv sink; - /* Temporary for immediate constants. */ - TCGv lit; }; /* Target-specific return values from translate_one, indicating the @@ -157,7 +155,7 @@ void alpha_translate_init(void) static TCGv load_zero(DisasContext *ctx) { if (!ctx->zero) { - ctx->zero = tcg_const_i64(0); + ctx->zero = tcg_constant_i64(0); } return ctx->zero; } @@ -177,14 +175,6 @@ static void free_context_temps(DisasContext *ctx) tcg_temp_free(ctx->sink); ctx->sink = NULL; } - if (ctx->zero) { - tcg_temp_free(ctx->zero); - ctx->zero = NULL; - } - if (ctx->lit) { - tcg_temp_free(ctx->lit); - ctx->lit = NULL; - } } static TCGv load_gpr(DisasContext *ctx, unsigned reg) @@ -200,8 +190,7 @@ static TCGv load_gpr_lit(DisasContext *ctx, unsigned reg, uint8_t lit, bool islit) { if (islit) { - ctx->lit = tcg_const_i64(lit); - return ctx->lit; + return tcg_constant_i64(lit); } else if (likely(reg < 31)) { return ctx->ir[reg]; } else { @@ -2992,7 +2981,6 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) ctx->zero = NULL; ctx->sink = NULL; - ctx->lit = NULL; /* Bound the number of insns to execute to those left on the page. */ bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; -- cgit v1.1 From 904bd855d38f8deb3f85a63d19475bb4a0c0d1a4 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 7 Jul 2021 18:54:44 -0700 Subject: target/alpha: Use tcg_constant_* elsewhere MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the remaining uses of tcg_const_*. These uses are all local, with the allocate and free close together. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 46 ++++++++++++++-------------------------------- 1 file changed, 14 insertions(+), 32 deletions(-) (limited to 'target') diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 58c0e08..103c632 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -250,11 +250,9 @@ static void gen_excp_1(int exception, int error_code) { TCGv_i32 tmp1, tmp2; - tmp1 = tcg_const_i32(exception); - tmp2 = tcg_const_i32(error_code); + tmp1 = tcg_constant_i32(exception); + tmp2 = tcg_constant_i32(error_code); gen_helper_excp(cpu_env, tmp1, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp1); } static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code) @@ -474,15 +472,11 @@ static DisasJumpType gen_bcond_internal(DisasContext *ctx, TCGCond cond, return DISAS_NORETURN; } else { - TCGv_i64 z = tcg_const_i64(0); - TCGv_i64 d = tcg_const_i64(dest); - TCGv_i64 p = tcg_const_i64(ctx->base.pc_next); + TCGv_i64 z = load_zero(ctx); + TCGv_i64 d = tcg_constant_i64(dest); + TCGv_i64 p = tcg_constant_i64(ctx->base.pc_next); tcg_gen_movcond_i64(cond, cpu_pc, cmp, z, d, p); - - tcg_temp_free_i64(z); - tcg_temp_free_i64(d); - tcg_temp_free_i64(p); return DISAS_PC_UPDATED; } } @@ -684,22 +678,19 @@ static void gen_fp_exc_raise(int rc, int fn11) if (!(fn11 & QUAL_I)) { ignore |= FPCR_INE; } - ign = tcg_const_i32(ignore); + ign = tcg_constant_i32(ignore); /* ??? Pass in the regno of the destination so that the helper can set EXC_MASK, which contains a bitmask of destination registers that have caused arithmetic traps. A simple userspace emulation does not require this. We do need it for a guest kernel's entArith, or if we were to do something clever with imprecise exceptions. */ - reg = tcg_const_i32(rc + 32); + reg = tcg_constant_i32(rc + 32); if (fn11 & QUAL_S) { gen_helper_fp_exc_raise_s(cpu_env, ign, reg); } else { gen_helper_fp_exc_raise(cpu_env, ign, reg); } - - tcg_temp_free_i32(reg); - tcg_temp_free_i32(ign); } static void gen_cvtlq(TCGv vc, TCGv vb) @@ -792,7 +783,7 @@ IEEE_INTCVT(cvtqt) static void gen_cpy_mask(TCGv vc, TCGv va, TCGv vb, bool inv_a, uint64_t mask) { - TCGv vmask = tcg_const_i64(mask); + TCGv vmask = tcg_constant_i64(mask); TCGv tmp = tcg_temp_new_i64(); if (inv_a) { @@ -804,7 +795,6 @@ static void gen_cpy_mask(TCGv vc, TCGv va, TCGv vb, bool inv_a, uint64_t mask) tcg_gen_andc_i64(vc, vb, vmask); tcg_gen_or_i64(vc, vc, tmp); - tcg_temp_free(vmask); tcg_temp_free(tmp); } @@ -1178,12 +1168,9 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) case 0x3E: /* WTINT */ - { - TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) + - offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp); - } + tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + -offsetof(AlphaCPU, env) + + offsetof(CPUState, halted)); tcg_gen_movi_i64(ctx->ir[IR_V0], 0); return gen_excp(ctx, EXCP_HALTED, 0); @@ -1334,12 +1321,8 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno) case 253: /* WAIT */ - { - TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) + - offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp); - } + tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + -offsetof(AlphaCPU, env) + offsetof(CPUState, halted)); return gen_excp(ctx, EXCP_HALTED, 0); case 252: @@ -2712,9 +2695,8 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) vb = load_gpr(ctx, rb); } tcg_gen_movi_i64(cpu_lock_addr, -1); + st_flag_byte(load_zero(ctx), ENV_FLAG_RX_SHIFT); tmp = tcg_temp_new(); - tcg_gen_movi_i64(tmp, 0); - st_flag_byte(tmp, ENV_FLAG_RX_SHIFT); tcg_gen_andi_i64(tmp, vb, 1); st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT); tcg_temp_free(tmp); -- cgit v1.1 From af42d3540179d48ee31bd421d00100c26bfb63e3 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 8 Jul 2021 14:05:03 -0700 Subject: target/openrisc: Use tcg_constant_* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace uses of tcg_const_* allocate and free close together with tcg_constant_*. Reviewed-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 42 +++++++++--------------------------------- 1 file changed, 9 insertions(+), 33 deletions(-) (limited to 'target') diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 37c3e3e..1e3b019 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -129,9 +129,7 @@ void openrisc_translate_init(void) static void gen_exception(DisasContext *dc, unsigned int excp) { - TCGv_i32 tmp = tcg_const_i32(excp); - gen_helper_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_exception(cpu_env, tcg_constant_i32(excp)); } static void gen_illegal_exception(DisasContext *dc) @@ -538,13 +536,11 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a) static bool trans_l_cmov(DisasContext *dc, arg_dab *a) { - TCGv zero; + TCGv zero = tcg_constant_tl(0); check_r0_write(dc, a->d); - zero = tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero, cpu_R(dc, a->a), cpu_R(dc, a->b)); - tcg_temp_free(zero); return true; } @@ -632,15 +628,11 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) { target_ulong tmp_pc = dc->base.pc_next + a->n * 4; - TCGv t_next = tcg_const_tl(dc->base.pc_next + 8); - TCGv t_true = tcg_const_tl(tmp_pc); - TCGv t_zero = tcg_const_tl(0); + TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8); + TCGv t_true = tcg_constant_tl(tmp_pc); + TCGv t_zero = tcg_constant_tl(0); tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next); - - tcg_temp_free(t_next); - tcg_temp_free(t_true); - tcg_temp_free(t_zero); dc->delayed_branch = 2; } @@ -813,44 +805,28 @@ static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a) static bool trans_l_addi(DisasContext *dc, arg_rri *a) { - TCGv t0; - check_r0_write(dc, a->d); - t0 = tcg_const_tl(a->i); - gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); - tcg_temp_free(t0); + gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); return true; } static bool trans_l_addic(DisasContext *dc, arg_rri *a) { - TCGv t0; - check_r0_write(dc, a->d); - t0 = tcg_const_tl(a->i); - gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); - tcg_temp_free(t0); + gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); return true; } static bool trans_l_muli(DisasContext *dc, arg_rri *a) { - TCGv t0; - check_r0_write(dc, a->d); - t0 = tcg_const_tl(a->i); - gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); - tcg_temp_free(t0); + gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); return true; } static bool trans_l_maci(DisasContext *dc, arg_l_maci *a) { - TCGv t0; - - t0 = tcg_const_tl(a->i); - gen_mac(dc, cpu_R(dc, a->a), t0); - tcg_temp_free(t0); + gen_mac(dc, cpu_R(dc, a->a), tcg_constant_tl(a->i)); return true; } -- cgit v1.1 From 4d10fa0ff901b055ca75f6986974609bc99820dd Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 8 Jul 2021 14:12:09 -0700 Subject: target/openrisc: Use tcg_constant_tl for dc->R0 The temp allocated for tcg_const_tl is auto-freed at branches, but pure constants are not. So we can remove the extra hoop jumping in trans_l_swa. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'target') diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 1e3b019..2db529b 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -732,12 +732,6 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) ea = tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); - /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned - to cpu_regs[0]. Since l.swa is quite often immediately followed by a - branch, don't bother reallocating; finish the TB using the "real" R0. - This also takes care of RB input across the branch. */ - dc->R0 = cpu_regs[0]; - lab_fail = gen_new_label(); lab_done = gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); @@ -745,7 +739,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) val = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, - cpu_regs[a->b], dc->mem_idx, MO_TEUL); + cpu_R(dc, a->b), dc->mem_idx, MO_TEUL); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); tcg_temp_free(val); @@ -1601,7 +1595,7 @@ static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) /* Allow the TCG optimizer to see that R0 == 0, when it's true, which is the common case. */ if (dc->tb_flags & TB_FLAGS_R0_0) { - dc->R0 = tcg_const_tl(0); + dc->R0 = tcg_constant_tl(0); } else { dc->R0 = cpu_regs[0]; } -- cgit v1.1 From 118671f02faf4d67f283731eafc96bb72b125431 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 8 Jul 2021 14:15:56 -0700 Subject: target/openrisc: Cache constant 0 in DisasContext MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are virtually certain to have fetched constant 0 once, at the beginning of the TB, so we might as well use it elsewhere. Reviewed-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'target') diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 2db529b..6aba4c2 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -52,6 +52,8 @@ typedef struct DisasContext { /* The temporary corresponding to register 0 for this compilation. */ TCGv R0; + /* The constant zero. */ + TCGv zero; } DisasContext; static inline bool is_user(DisasContext *dc) @@ -536,10 +538,8 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a) static bool trans_l_cmov(DisasContext *dc, arg_dab *a) { - TCGv zero = tcg_constant_tl(0); - check_r0_write(dc, a->d); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero, + tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } @@ -630,9 +630,8 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) target_ulong tmp_pc = dc->base.pc_next + a->n * 4; TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8); TCGv t_true = tcg_constant_tl(tmp_pc); - TCGv t_zero = tcg_constant_tl(0); - tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next); + tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next); dc->delayed_branch = 2; } @@ -1594,8 +1593,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) /* Allow the TCG optimizer to see that R0 == 0, when it's true, which is the common case. */ + dc->zero = tcg_constant_tl(0); if (dc->tb_flags & TB_FLAGS_R0_0) { - dc->R0 = tcg_constant_tl(0); + dc->R0 = dc->zero; } else { dc->R0 = cpu_regs[0]; } -- cgit v1.1 From e0efc48fbc6ed9f308fbbff394c5c1044067909f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 8 Jul 2021 14:34:29 -0700 Subject: target/openrisc: Use dc->zero in gen_add, gen_addc We still need the t0 temporary for computing overflow, but we do not need to initialize it to zero first. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'target') diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 6aba4c2..059da48 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -199,10 +199,10 @@ static void gen_ove_cyov(DisasContext *dc) static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv t0 = tcg_const_tl(0); + TCGv t0 = tcg_temp_new(); TCGv res = tcg_temp_new(); - tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0); + tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, srcb, dc->zero); tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); @@ -216,11 +216,11 @@ static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv t0 = tcg_const_tl(0); + TCGv t0 = tcg_temp_new(); TCGv res = tcg_temp_new(); - tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0); - tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0); + tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, cpu_sr_cy, dc->zero); + tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, dc->zero); tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); -- cgit v1.1 From 29dd6f644a7b8a5a9a8bc249a25d50bc0e266da9 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 8 Jul 2021 12:41:29 -0700 Subject: target/hppa: Use tcg_constant_* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace uses of tcg_const_* with the allocate and free close together. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 56 ++++++++++++++++--------------------------------- 1 file changed, 18 insertions(+), 38 deletions(-) (limited to 'target') diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 835120c..fa66807 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -144,6 +144,7 @@ #define tcg_gen_sextract_reg tcg_gen_sextract_i64 #define tcg_const_reg tcg_const_i64 #define tcg_const_local_reg tcg_const_local_i64 +#define tcg_constant_reg tcg_constant_i64 #define tcg_gen_movcond_reg tcg_gen_movcond_i64 #define tcg_gen_add2_reg tcg_gen_add2_i64 #define tcg_gen_sub2_reg tcg_gen_sub2_i64 @@ -238,6 +239,7 @@ #define tcg_gen_sextract_reg tcg_gen_sextract_i32 #define tcg_const_reg tcg_const_i32 #define tcg_const_local_reg tcg_const_local_i32 +#define tcg_constant_reg tcg_constant_i32 #define tcg_gen_movcond_reg tcg_gen_movcond_i32 #define tcg_gen_add2_reg tcg_gen_add2_i32 #define tcg_gen_sub2_reg tcg_gen_sub2_i32 @@ -771,9 +773,7 @@ static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) static void gen_excp_1(int exception) { - TCGv_i32 t = tcg_const_i32(exception); - gen_helper_excp(cpu_env, t); - tcg_temp_free_i32(t); + gen_helper_excp(cpu_env, tcg_constant_i32(exception)); } static void gen_excp(DisasContext *ctx, int exception) @@ -787,12 +787,9 @@ static void gen_excp(DisasContext *ctx, int exception) static bool gen_excp_iir(DisasContext *ctx, int exc) { - TCGv_reg tmp; - nullify_over(ctx); - tmp = tcg_const_reg(ctx->insn); - tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); - tcg_temp_free(tmp); + tcg_gen_st_reg(tcg_constant_reg(ctx->insn), + cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); gen_excp(ctx, exc); return nullify_end(ctx); } @@ -1150,13 +1147,12 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, } if (!is_l || cond_need_cb(c)) { - TCGv_reg zero = tcg_const_reg(0); + TCGv_reg zero = tcg_constant_reg(0); cb_msb = get_temp(ctx); tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); if (is_c) { tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero); } - tcg_temp_free(zero); if (!is_l) { cb = get_temp(ctx); tcg_gen_xor_reg(cb, in1, in2); @@ -1242,7 +1238,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, cb = tcg_temp_new(); cb_msb = tcg_temp_new(); - zero = tcg_const_reg(0); + zero = tcg_constant_reg(0); if (is_b) { /* DEST,C = IN1 + ~IN2 + C. */ tcg_gen_not_reg(cb, in2); @@ -1258,7 +1254,6 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, tcg_gen_eqv_reg(cb, in1, in2); tcg_gen_xor_reg(cb, cb, dest); } - tcg_temp_free(zero); /* Compute signed overflow if required. */ sv = NULL; @@ -2449,17 +2444,16 @@ static bool trans_probe(DisasContext *ctx, arg_probe *a) form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); if (a->imm) { - level = tcg_const_i32(a->ri); + level = tcg_constant_i32(a->ri); } else { level = tcg_temp_new_i32(); tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri)); tcg_gen_andi_i32(level, level, 3); } - want = tcg_const_i32(a->write ? PAGE_WRITE : PAGE_READ); + want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); gen_helper_probe(dest, cpu_env, addr, level, want); - tcg_temp_free_i32(want); tcg_temp_free_i32(level); save_gpr(ctx, a->t, dest); @@ -2599,17 +2593,13 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a) static bool trans_lci(DisasContext *ctx, arg_lci *a) { - TCGv_reg ci; - CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); /* The Coherence Index is an implementation-defined function of the physical address. Two addresses with the same CI have a coherent view of the cache. Our implementation is to return 0 for all, since the entire address space is coherent. */ - ci = tcg_const_reg(0); - save_gpr(ctx, a->t, ci); - tcg_temp_free(ci); + save_gpr(ctx, a->t, tcg_constant_reg(0)); cond_free(&ctx->null_cond); return true; @@ -2710,8 +2700,6 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) * currently implemented as idle. */ if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ - TCGv_i32 tmp; - /* No need to check for supervisor, as userland can only pause until the next timer interrupt. */ nullify_over(ctx); @@ -2722,10 +2710,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ - tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + - offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp); + tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + offsetof(CPUState, halted) - offsetof(HPPACPU, env)); gen_excp_1(EXCP_HALTED); ctx->base.is_jmp = DISAS_NORETURN; @@ -2833,7 +2819,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) add2 = tcg_temp_new(); addc = tcg_temp_new(); dest = tcg_temp_new(); - zero = tcg_const_reg(0); + zero = tcg_constant_reg(0); /* Form R1 << 1 | PSW[CB]{8}. */ tcg_gen_add_reg(add1, in1, in1); @@ -2851,7 +2837,6 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero); tcg_temp_free(addc); - tcg_temp_free(zero); /* Write back the result register. */ save_gpr(ctx, a->t, dest); @@ -2967,9 +2952,8 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) */ gen_helper_ldc_check(addr); - zero = tcg_const_reg(0); + zero = tcg_constant_reg(0); tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); - tcg_temp_free(zero); if (a->m) { save_gpr(ctx, a->b, ofs); @@ -3882,15 +3866,13 @@ static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a) ta = load_frw0_i32(a->r1); tb = load_frw0_i32(a->r2); - ty = tcg_const_i32(a->y); - tc = tcg_const_i32(a->c); + ty = tcg_constant_i32(a->y); + tc = tcg_constant_i32(a->c); gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc); tcg_temp_free_i32(ta); tcg_temp_free_i32(tb); - tcg_temp_free_i32(ty); - tcg_temp_free_i32(tc); return nullify_end(ctx); } @@ -3904,15 +3886,13 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) ta = load_frd0(a->r1); tb = load_frd0(a->r2); - ty = tcg_const_i32(a->y); - tc = tcg_const_i32(a->c); + ty = tcg_constant_i32(a->y); + tc = tcg_constant_i32(a->c); gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc); tcg_temp_free_i64(ta); tcg_temp_free_i64(tb); - tcg_temp_free_i32(ty); - tcg_temp_free_i32(tc); return nullify_end(ctx); } -- cgit v1.1 From 6e94937a54c6ef80c3f523d8560c8b6521e6c79c Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 8 Jul 2021 13:54:36 -0700 Subject: target/hppa: Clean up DisasCond The a0_is_n flag is redundant with comparing a0 to cpu_psw_n. The a1_is_0 flag can be removed by initializing a1 to $0, which also means that cond_prep can be removed entirely. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 43 +++++++++---------------------------------- 1 file changed, 9 insertions(+), 34 deletions(-) (limited to 'target') diff --git a/target/hppa/translate.c b/target/hppa/translate.c index fa66807..2552747 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -252,8 +252,6 @@ typedef struct DisasCond { TCGCond c; TCGv_reg a0, a1; - bool a0_is_n; - bool a1_is_0; } DisasCond; typedef struct DisasContext { @@ -448,9 +446,7 @@ static DisasCond cond_make_n(void) return (DisasCond){ .c = TCG_COND_NE, .a0 = cpu_psw_n, - .a0_is_n = true, - .a1 = NULL, - .a1_is_0 = true + .a1 = tcg_constant_reg(0) }; } @@ -458,7 +454,7 @@ static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) { assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); return (DisasCond){ - .c = c, .a0 = a0, .a1_is_0 = true + .c = c, .a0 = a0, .a1 = tcg_constant_reg(0) }; } @@ -482,26 +478,14 @@ static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) return r; } -static void cond_prep(DisasCond *cond) -{ - if (cond->a1_is_0) { - cond->a1_is_0 = false; - cond->a1 = tcg_const_reg(0); - } -} - static void cond_free(DisasCond *cond) { switch (cond->c) { default: - if (!cond->a0_is_n) { + if (cond->a0 != cpu_psw_n) { tcg_temp_free(cond->a0); } - if (!cond->a1_is_0) { - tcg_temp_free(cond->a1); - } - cond->a0_is_n = false; - cond->a1_is_0 = false; + tcg_temp_free(cond->a1); cond->a0 = NULL; cond->a1 = NULL; /* fallthru */ @@ -559,9 +543,8 @@ static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) { if (ctx->null_cond.c != TCG_COND_NEVER) { - cond_prep(&ctx->null_cond); tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, - ctx->null_cond.a1, dest, t); + ctx->null_cond.a1, dest, t); } else { tcg_gen_mov_reg(dest, t); } @@ -668,11 +651,9 @@ static void nullify_over(DisasContext *ctx) assert(ctx->null_cond.c != TCG_COND_ALWAYS); ctx->null_lab = gen_new_label(); - cond_prep(&ctx->null_cond); /* If we're using PSW[N], copy it to a temp because... */ - if (ctx->null_cond.a0_is_n) { - ctx->null_cond.a0_is_n = false; + if (ctx->null_cond.a0 == cpu_psw_n) { ctx->null_cond.a0 = tcg_temp_new(); tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); } @@ -685,7 +666,7 @@ static void nullify_over(DisasContext *ctx) } tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, - ctx->null_cond.a1, ctx->null_lab); + ctx->null_cond.a1, ctx->null_lab); cond_free(&ctx->null_cond); } } @@ -699,10 +680,9 @@ static void nullify_save(DisasContext *ctx) } return; } - if (!ctx->null_cond.a0_is_n) { - cond_prep(&ctx->null_cond); + if (ctx->null_cond.a0 != cpu_psw_n) { tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, - ctx->null_cond.a0, ctx->null_cond.a1); + ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero = true; } cond_free(&ctx->null_cond); @@ -1178,7 +1158,6 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, /* Emit any conditional trap before any writeback. */ cond = do_cond(cf, dest, cb_msb, sv); if (is_tc) { - cond_prep(&cond); tmp = tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); @@ -1273,7 +1252,6 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, /* Emit any conditional trap before any writeback. */ if (is_tc) { - cond_prep(&cond); tmp = tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); @@ -1399,7 +1377,6 @@ static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, if (is_tc) { TCGv_reg tmp = tcg_temp_new(); - cond_prep(&cond); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); @@ -1855,7 +1832,6 @@ static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, } taken = gen_new_label(); - cond_prep(cond); tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); cond_free(cond); @@ -1952,7 +1928,6 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest, tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx); } else { - cond_prep(&ctx->null_cond); c = ctx->null_cond.c; a0 = ctx->null_cond.a0; a1 = ctx->null_cond.a1; -- cgit v1.1