From 00d312bd78c91650e05b6e9676650db6865576f0 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Tue, 7 Mar 2023 16:14:03 +0800 Subject: target/riscv: Add support for Zce Add and expose property for Zce: * Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt. * Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 12 ++++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 13 insertions(+) (limited to 'target') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ed8dc61..cd9e7bd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -91,6 +91,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), + ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce), ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), @@ -945,6 +946,16 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } + if (cpu->cfg.ext_zce) { + cpu->cfg.ext_zca = true; + cpu->cfg.ext_zcb = true; + cpu->cfg.ext_zcmp = true; + cpu->cfg.ext_zcmt = true; + if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { + cpu->cfg.ext_zcf = true; + } + } + if (cpu->cfg.ext_c) { cpu->cfg.ext_zca = true; if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { @@ -1501,6 +1512,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), + DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8d66365..5f38b0a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -443,6 +443,7 @@ struct RISCVCPUConfig { bool ext_zca; bool ext_zcb; bool ext_zcd; + bool ext_zce; bool ext_zcf; bool ext_zcmp; bool ext_zcmt; -- cgit v1.1