From 74433bf083b0766aba81534f92de13194f23ff3e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 11:51:19 -0700 Subject: tcg: Split out target/arch/cpu-param.h For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- target/sparc/cpu-param.h | 28 ++++++++++++++++++++++++++++ target/sparc/cpu.h | 20 ++------------------ 2 files changed, 30 insertions(+), 18 deletions(-) create mode 100644 target/sparc/cpu-param.h (limited to 'target/sparc') diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h new file mode 100644 index 0000000..4746d89 --- /dev/null +++ b/target/sparc/cpu-param.h @@ -0,0 +1,28 @@ +/* + * Sparc cpu parameters for qemu. + * + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef SPARC_CPU_PARAM_H +#define SPARC_CPU_PARAM_H 1 + +#ifdef TARGET_SPARC64 +# define TARGET_LONG_BITS 64 +# define TARGET_PAGE_BITS 13 /* 8k */ +# define TARGET_PHYS_ADDR_SPACE_BITS 41 +# ifdef TARGET_ABI32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 44 +# endif +# define NB_MMU_MODES 6 +#else +# define TARGET_LONG_BITS 32 +# define TARGET_PAGE_BITS 12 /* 4k */ +# define TARGET_PHYS_ADDR_SPACE_BITS 36 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +# define NB_MMU_MODES 3 +#endif + +#endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index f31e853..bcfdf51 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,31 +4,18 @@ #include "qemu-common.h" #include "qemu/bswap.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" #define ALIGNED_ONLY #if !defined(TARGET_SPARC64) -#define TARGET_LONG_BITS 32 #define TARGET_DPREGS 16 -#define TARGET_PAGE_BITS 12 /* 4k */ -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 #else -#define TARGET_LONG_BITS 64 #define TARGET_DPREGS 32 -#define TARGET_PAGE_BITS 13 /* 8k */ -#define TARGET_PHYS_ADDR_SPACE_BITS 41 -# ifdef TARGET_ABI32 -# define TARGET_VIRT_ADDR_SPACE_BITS 32 -# else -# define TARGET_VIRT_ADDR_SPACE_BITS 44 -# endif #endif #define CPUArchState struct CPUSPARCState -#include "exec/cpu-defs.h" - /*#define EXCP_INTERRUPT 0x100*/ /* trap definitions */ @@ -225,10 +212,7 @@ enum { #define MIN_NWINDOWS 3 #define MAX_NWINDOWS 32 -#if !defined(TARGET_SPARC64) -#define NB_MMU_MODES 3 -#else -#define NB_MMU_MODES 6 +#ifdef TARGET_SPARC64 typedef struct trap_state { uint64_t tpc; uint64_t tnpc; -- cgit v1.1 From 4f7c64b3819d559417615ed2b1d028ebc1a49580 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 15:32:23 -0700 Subject: cpu: Define CPUArchState with typedef For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/sparc') diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index bcfdf51..fc392c6 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -14,8 +14,6 @@ #define TARGET_DPREGS 32 #endif -#define CPUArchState struct CPUSPARCState - /*#define EXCP_INTERRUPT 0x100*/ /* trap definitions */ @@ -731,6 +729,8 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) #endif } +typedef CPUSPARCState CPUArchState; + #include "exec/cpu-all.h" #ifdef TARGET_SPARC64 -- cgit v1.1 From 2161a612b4e1d388046320bc464adefd6bba01a0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 15:56:19 -0700 Subject: cpu: Define ArchCPU For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target/sparc') diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index fc392c6..ba5904e 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -730,6 +730,7 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) } typedef CPUSPARCState CPUArchState; +typedef SPARCCPU ArchCPU; #include "exec/cpu-all.h" -- cgit v1.1 From 29a0af618ddd21f55df5753c3e16b0625f534b3c Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 16:07:18 -0700 Subject: cpu: Replace ENV_GET_CPU with env_cpu Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'target/sparc') diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ba5904e..e294213 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -537,8 +537,6 @@ static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) return container_of(env, SPARCCPU, env); } -#define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) - #define ENV_OFFSET offsetof(SPARCCPU, env) #ifndef CONFIG_USER_ONLY -- cgit v1.1 From 5a59fbce9141c40db0f0a5a6e17583ad9189b48b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 19:36:20 -0700 Subject: target/sparc: Use env_cpu, env_archcpu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cleanup in the boilerplate that each target must define. Replace sparc_env_get_cpu with env_archcpu. The combination CPU(sparc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 5 ----- target/sparc/fop_helper.c | 2 +- target/sparc/helper.c | 8 ++++---- target/sparc/ldst_helper.c | 33 +++++++++++++++------------------ target/sparc/mmu_helper.c | 10 +++++----- 5 files changed, 25 insertions(+), 33 deletions(-) (limited to 'target/sparc') diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index e294213..adcd9e3 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -532,11 +532,6 @@ struct SPARCCPU { CPUSPARCState env; }; -static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) -{ - return container_of(env, SPARCCPU, env); -} - #define ENV_OFFSET offsetof(SPARCCPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index b6642fd..9eb9b75 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -53,7 +53,7 @@ static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) } if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); /* Unmasked exception, generate a trap. Note that while the helper is marked as NO_WG, we can get away with diff --git a/target/sparc/helper.c b/target/sparc/helper.c index 4623278..1a52061 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -26,7 +26,7 @@ void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = tt; cpu_loop_exit_restore(cs, ra); @@ -34,7 +34,7 @@ void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra) void helper_raise_exception(CPUSPARCState *env, int tt) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = tt; cpu_loop_exit(cs); @@ -42,7 +42,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt) void helper_debug(CPUSPARCState *env) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = EXCP_DEBUG; cpu_loop_exit(cs); @@ -243,7 +243,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, #ifndef TARGET_SPARC64 void helper_power_down(CPUSPARCState *env) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->halted = 1; cs->exception_index = EXCP_HLT; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index b4bf6fa..7f56c10 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -122,13 +122,13 @@ static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) static void replace_tlb_entry(SparcTLBEntry *tlb, uint64_t tlb_tag, uint64_t tlb_tte, - CPUSPARCState *env1) + CPUSPARCState *env) { target_ulong mask, size, va, offset; /* flush page range if translation is valid */ if (TTE_IS_VALID(tlb->tte)) { - CPUState *cs = CPU(sparc_env_get_cpu(env1)); + CPUState *cs = env_cpu(env); size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); mask = 1ULL + ~size; @@ -499,7 +499,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, { int size = 1 << (memop & MO_SIZE); int sign = memop & MO_SIGN; - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint64_t ret = 0; #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) uint32_t last_addr = addr; @@ -725,8 +725,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, uint32_t memop) { int size = 1 << (memop & MO_SIZE); - SPARCCPU *cpu = sparc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); do_check_align(env, addr, size - 1, GETPC()); switch (asi) { @@ -874,13 +873,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, DPRINTF_MMU("mmu flush level %d\n", mmulev); switch (mmulev) { case 0: /* flush page */ - tlb_flush_page(CPU(cpu), addr & 0xfffff000); + tlb_flush_page(cs, addr & 0xfffff000); break; case 1: /* flush segment (256k) */ case 2: /* flush region (16M) */ case 3: /* flush context (4G) */ case 4: /* flush entire */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; default: break; @@ -905,7 +904,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, are invalid in normal mode. */ if ((oldreg ^ env->mmuregs[reg]) & (MMU_NF | env->def.mmu_bm)) { - tlb_flush(CPU(cpu)); + tlb_flush(cs); } break; case 1: /* Context Table Pointer Register */ @@ -916,7 +915,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, if (oldreg != env->mmuregs[reg]) { /* we flush when the MMU context changes because QEMU has no MMU context support */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); } break; case 3: /* Synchronous Fault Status Register with Clear */ @@ -1027,8 +1026,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, case ASI_USERTXT: /* User code access, XXX */ case ASI_KERNELTXT: /* Supervisor code access, XXX */ default: - cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), - addr, true, false, asi, size); + cpu_unassigned_access(cs, addr, true, false, asi, size); break; case ASI_USERDATA: /* User data access */ @@ -1175,7 +1173,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, { int size = 1 << (memop & MO_SIZE); int sign = memop & MO_SIGN; - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint64_t ret = 0; #if defined(DEBUG_ASI) target_ulong last_addr = addr; @@ -1481,8 +1479,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, int asi, uint32_t memop) { int size = 1 << (memop & MO_SIZE); - SPARCCPU *cpu = sparc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); #ifdef DEBUG_ASI dump_asi("write", addr, asi, size, val); @@ -1686,13 +1683,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, env->dmmu.mmu_primary_context = val; /* can be optimized to only flush MMU_USER_IDX and MMU_KERNEL_IDX entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 2: /* Secondary context */ env->dmmu.mmu_secondary_context = val; /* can be optimized to only flush MMU_USER_SECONDARY_IDX and MMU_KERNEL_SECONDARY_IDX entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 5: /* TSB access */ DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" @@ -1768,13 +1765,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, case 1: env->dmmu.mmu_primary_context = val; env->immu.mmu_primary_context = val; - tlb_flush_by_mmuidx(CPU(cpu), + tlb_flush_by_mmuidx(cs, (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX)); break; case 2: env->dmmu.mmu_secondary_context = val; env->immu.mmu_secondary_context = val; - tlb_flush_by_mmuidx(CPU(cpu), + tlb_flush_by_mmuidx(cs, (1 << MMU_USER_SECONDARY_IDX) | (1 << MMU_KERNEL_SECONDARY_IDX)); break; diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index facc0c6..cbd1e91 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -97,7 +97,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, uint32_t pde; int error_code = 0, is_dirty, is_user; unsigned long page_offset; - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); is_user = mmu_idx == MMU_USER_IDX; @@ -268,7 +268,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); hwaddr pde_ptr; uint32_t pde; @@ -335,7 +335,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) void dump_mmu(CPUSPARCState *env) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_ulong va, va1, va2; unsigned int n, m, o; hwaddr pde_ptr, pa; @@ -494,7 +494,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int mmu_idx) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); unsigned int i; uint64_t context; uint64_t sfsr = 0; @@ -612,7 +612,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int mmu_idx) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); unsigned int i; uint64_t context; bool is_user = false; -- cgit v1.1 From 677c4d69ac21961e76a386f9bfc892a44923acc0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 17:00:56 -0700 Subject: cpu: Move ENV_OFFSET to exec/gen-icount.h Now that we have ArchCPU, we can define this generically, in the one place that needs it. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 - 1 file changed, 1 deletion(-) (limited to 'target/sparc') diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index adcd9e3..0cc3687 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -532,7 +532,6 @@ struct SPARCCPU { CPUSPARCState env; }; -#define ENV_OFFSET offsetof(SPARCCPU, env) #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_sparc_cpu; -- cgit v1.1 From 7506ed902eb97fe4e2a1dd16766c621d32ecc40d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 28 Mar 2019 11:26:22 -1000 Subject: cpu: Introduce cpu_set_cpustate_pointers Consolidate some boilerplate from foo_cpu_initfn. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'target/sparc') diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index f93ce72..ad2c362 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -774,12 +774,11 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) static void sparc_cpu_initfn(Object *obj) { - CPUState *cs = CPU(obj); SPARCCPU *cpu = SPARC_CPU(obj); SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); CPUSPARCState *env = &cpu->env; - cs->env_ptr = env; + cpu_set_cpustate_pointers(cpu); if (scc->cpu_def) { env->def = *scc->cpu_def; -- cgit v1.1 From 5b146dc716cfd247f99556c04e6e46fbd67565a0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 17:16:06 -0700 Subject: cpu: Introduce CPUNegativeOffsetState Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target/sparc') diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 0cc3687..a3c4f47 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -529,6 +529,7 @@ struct SPARCCPU { CPUState parent_obj; /*< public >*/ + CPUNegativeOffsetState neg; CPUSPARCState env; }; -- cgit v1.1 From e8b5fae5161c48e0d0e8b35eaf9dd8f35d692088 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 23 Mar 2019 11:35:53 -0700 Subject: cpu: Remove CPU_COMMON This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'target/sparc') diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index a3c4f47..49e0349 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -446,8 +446,6 @@ struct CPUSPARCState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; - CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ target_ulong version; uint32_t nwindows; -- cgit v1.1