From f9e580c13ae0d42cf8989063254300c59166ffed Mon Sep 17 00:00:00 2001 From: Emmanuel Blot Date: Fri, 16 Apr 2021 16:17:11 +0200 Subject: target/riscv: fix exception index on instruction access fault When no MMU is used and the guest code attempts to fetch an instruction from an invalid memory location, the exception index defaults to a data load access fault, rather an instruction access fault. Signed-off-by: Emmanuel Blot Reviewed-by: Alistair Francis Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target/riscv') diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 659ca8a..1018c00 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -694,8 +694,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, if (access_type == MMU_DATA_STORE) { cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; - } else { + } else if (access_type == MMU_DATA_LOAD) { cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } else { + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; } env->badaddr = addr; -- cgit v1.1