From a555ad1399c9eda9da0c5f8e40acd94d87957054 Mon Sep 17 00:00:00 2001 From: Jonathan Behrens Date: Mon, 14 Oct 2019 11:45:27 -0400 Subject: target/riscv: Tell gdbstub the correct number of CSRs If the number of registers reported to the gdbstub code does not match the number in the associated XML file, then the register numbers used by the stub may get out of sync with a remote GDB instance. Signed-off-by: Jonathan Behrens Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/riscv') diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ded140e..cb5bfd3 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -384,7 +384,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-32bit-csr.xml", 0); + 240, "riscv-32bit-csr.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -392,6 +392,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-64bit-csr.xml", 0); + 240, "riscv-64bit-csr.xml", 0); #endif } -- cgit v1.1