From 87b27bfca432c69a2abfd7a9ebc1fa27876b31f5 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Thu, 15 Jun 2023 14:32:59 +0800 Subject: target/riscv: Add support for Zvfbfmin extension Add trans_* and helper function for Zvfbfmin instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Message-Id: <20230615063302.102409-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target/riscv/vector_helper.c') diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1e06e74..4d2bd42 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4535,6 +4535,9 @@ RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64) GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 4) GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 8) +RVVCALL(OPFVV1, vfwcvtbf16_f_f_v, WOP_UU_H, H4, H2, bfloat16_to_float32) +GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v, 4) + /* Narrowing Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ #define NOP_UU_B uint8_t, uint16_t, uint32_t @@ -4581,6 +4584,9 @@ RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32) GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2) GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4) +RVVCALL(OPFVV1, vfncvtbf16_f_f_w, NOP_UU_H, H2, H4, float32_to_bfloat16) +GEN_VEXT_V_ENV(vfncvtbf16_f_f_w, 2) + /* * Vector Reduction Operations */ -- cgit v1.1