From 9495c4888a80809ab9dba6d6e536b21c018c77a4 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 9 Sep 2022 21:42:10 +0800 Subject: target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs, which allows us to support more types of triggers in the future. Signed-off-by: Frank Chang Reviewed-by: Bin Meng Signed-off-by: Bin Meng Reviewed-by: LIU Zhiwei Message-Id: <20220909134215.1843865-4-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/machine.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) (limited to 'target/riscv/machine.c') diff --git a/target/riscv/machine.c b/target/riscv/machine.c index a23cff4..c2a94a8 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -229,26 +229,16 @@ static bool debug_needed(void *opaque) return riscv_feature(env, RISCV_FEATURE_DEBUG); } -static const VMStateDescription vmstate_debug_type2 = { - .name = "cpu/debug/type2", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINTTL(mcontrol, type2_trigger_t), - VMSTATE_UINTTL(maddress, type2_trigger_t), - VMSTATE_END_OF_LIST() - } -}; - static const VMStateDescription vmstate_debug = { .name = "cpu/debug", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .needed = debug_needed, .fields = (VMStateField[]) { VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), - VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, RV_MAX_TRIGGERS, - 0, vmstate_debug_type2, type2_trigger_t), + VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), VMSTATE_END_OF_LIST() } }; -- cgit v1.1