From 1e2de2b8280a518a6178e7d4dda6c9906d8a86f2 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:52:05 -0300 Subject: target/riscv/cpu: remove CPUArchState::features and friends The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead. Remove env->feature, riscv_feature() and riscv_set_feature(). We also need to bump vmstate_riscv_cpu version_id and minimal_version_id since 'features' is no longer being migrated. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-11-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/machine.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'target/riscv/machine.c') diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 67e9e56..9c45593 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -331,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = { const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .version_id = 6, - .minimum_version_id = 6, + .version_id = 7, + .minimum_version_id = 7, .post_load = riscv_cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -351,7 +351,6 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT32(env.misa_ext, RISCVCPU), VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), - VMSTATE_UINT32(env.features, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.virt, RISCVCPU), VMSTATE_UINT64(env.resetvec, RISCVCPU), -- cgit v1.1