From e39a8320b088dd5efc9ebaafe387e52b3d962665 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 12 Aug 2020 12:13:49 -0700 Subject: target/riscv: Support the Virtual Instruction fault Signed-off-by: Alistair Francis Message-id: 4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com Message-Id: <4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com> --- target/riscv/insn_trans/trans_rvh.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/riscv/insn_trans') diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index db650ae..881c9ef 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -360,7 +360,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY - gen_helper_hyp_tlb_flush(cpu_env); + gen_helper_hyp_gvma_tlb_flush(cpu_env); return true; #endif return false; -- cgit v1.1