From c7b951718815694284501ed01fec7acb8654db7b Mon Sep 17 00:00:00 2001 From: Michael Clark Date: Fri, 4 Jan 2019 23:23:55 +0000 Subject: RISC-V: Implement modular CSR helper interface Previous CSR code uses csr_read_helper and csr_write_helper to update CSR registers however this interface prevents atomic read/modify/write CSR operations; in addition there is no trap-free method to access to CSRs due to the monolithic CSR functions call longjmp. The current iCSR interface is not safe to be called by target/riscv/gdbstub.c as privilege checks or missing CSRs may call longjmp to generate exceptions. It needs to indicate existence so traps can be generated in the CSR instruction helpers. This commit moves CSR access from the monolithic switch statements in target/riscv/op_helper.c into modular read/write functions in target/riscv/csr.c using a new function pointer table for dispatch (which can later be used to allow CPUs to hook up model specific CSRs). A read/modify/write interface is added to support atomic CSR operations and a non-trapping interface is added to allow exception-free access to CSRs by the debugger. The CSR functions and CSR dispatch table are ordered to match The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.10, 2.2 CSR Listing. An API is added to allow derived cpu instances to modify or implement new CSR operations. Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'target/riscv/gdbstub.c') diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 4f919b6..3cabb21 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -33,7 +33,10 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) } else if (n < 65) { return gdb_get_reg64(mem_buf, env->fpr[n - 33]); } else if (n < 4096 + 65) { - return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65)); + target_ulong val = 0; + if (riscv_csrrw(env, n - 65, &val, 0, 0) == 0) { + return gdb_get_regl(mem_buf, val); + } } return 0; } @@ -56,7 +59,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */ return sizeof(uint64_t); } else if (n < 4096 + 65) { - csr_write_helper(env, ldtul_p(mem_buf), n - 65); + target_ulong val = ldtul_p(mem_buf); + if (riscv_csrrw(env, n - 65, NULL, val, -1) == 0) { + return sizeof(target_ulong); + } } return 0; } -- cgit v1.1