From 6ffe9b6669757bc84bbb4c6218561823db431025 Mon Sep 17 00:00:00 2001 From: Alvin Chang Date: Mon, 26 Aug 2024 10:46:57 +0800 Subject: target/riscv: Add textra matching condition for the triggers According to RISC-V Debug specification, the optional textra32 and textra64 trigger CSRs can be used to configure additional matching conditions for the triggers. For example, if the textra.MHSELECT field is set to 4 (mcontext), this trigger will only match or fire if the low bits of mcontext/hcontext equal textra.MHVALUE field. This commit adds the aforementioned matching condition as common trigger matching conditions. Currently, the only legal values of textra.MHSELECT are 0 (ignore) and 4 (mcontext). When textra.MHSELECT is 0, we pass the checking. When textra.MHSELECT is 4, we compare textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis Message-ID: <20240826024657.262553-3-alvinga@andestech.com> Signed-off-by: Alistair Francis --- target/riscv/debug.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target/riscv/debug.h') diff --git a/target/riscv/debug.h b/target/riscv/debug.h index c347863..f76b8f9 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -131,6 +131,9 @@ enum { #define ITRIGGER_VU BIT(25) #define ITRIGGER_VS BIT(26) +#define MHSELECT_IGNORE 0 +#define MHSELECT_MCONTEXT 4 + bool tdata_available(CPURISCVState *env, int tdata_index); target_ulong tselect_csr_read(CPURISCVState *env); -- cgit v1.1