From 16fdb8ff64374ed51b246437e13043039a8eb9f9 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Sat, 20 Apr 2019 02:27:02 +0000 Subject: target/riscv: Improve the scause logic No functional change, just making the code easier to read. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/riscv/cpu_helper.c') diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7318da2..c577a26 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -515,7 +515,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_SPP, env->priv); s = set_field(s, MSTATUS_SIE, 0); env->mstatus = s; - env->scause = cause | ~(((target_ulong)-1) >> async); + env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); env->sepc = env->pc; env->sbadaddr = tval; env->pc = (env->stvec >> 2 << 2) + -- cgit v1.1