From c445593d30037d0c82241e8ec23eb845bca476e9 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 3 Nov 2020 20:43:23 -0800 Subject: target/riscv: Add a virtualised MMU Mode Add a new MMU mode that includes the current virt mode. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 4b301bc0ea36da962fc1605371b65019ac3073df.1604464950.git.alistair.francis@wdc.com --- target/riscv/cpu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target/riscv/cpu.h') diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 87b68af..5d8e54c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -363,7 +363,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); -#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MMU_MASK 7 +#define TB_FLAGS_PRIV_MMU_MASK 3 +#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS typedef CPURISCVState CPUArchState; -- cgit v1.1