From 9ec6622db30df1c00d863c1ffc33341f9e0a534d Mon Sep 17 00:00:00 2001
From: Frank Chang <frank.chang@sifive.com>
Date: Fri, 10 Dec 2021 15:55:47 +0800
Subject: target/riscv: drop vector 0.7.1 and add 1.0 support

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20211210075704.23951-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'target/riscv/cpu.h')

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ef677f9..5ea2004 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,7 +81,7 @@ enum {
 #define PRIV_VERSION_1_10_0 0x00011000
 #define PRIV_VERSION_1_11_0 0x00011100
 
-#define VEXT_VERSION_0_07_1 0x00000701
+#define VEXT_VERSION_1_00_0 0x00010000
 
 enum {
     TRANSLATE_SUCCESS,
-- 
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