From edf647864bdab84ed4b1a4f47ea05be6bb075c69 Mon Sep 17 00:00:00 2001 From: Sylvain Pelissier Date: Wed, 6 Jan 2021 21:41:41 +0100 Subject: gdb: riscv: Add target description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210106204141.14027-1-sylvain.pelissier@gmail.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'target/riscv/cpu.c') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8227d7a..6aafe4e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -557,6 +557,18 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static gchar *riscv_gdb_arch_name(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (riscv_cpu_is_32bit(env)) { + return g_strdup("riscv:rv32"); + } else { + return g_strdup("riscv:rv64"); + } +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -592,6 +604,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; #endif + cc->gdb_arch_name = riscv_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; -- cgit v1.1