From e523773040ed914b60c8b68c25a96c88b2bb112a Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:43:27 +0800 Subject: target/riscv: zfh: add Zfhmin cpu property Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-9-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target/riscv/cpu.c') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0f808a5..9835829 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -630,6 +630,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), + DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), -- cgit v1.1