From c1ad0b892ce20cf2b5e619c79e8a0c4c66b235dc Mon Sep 17 00:00:00 2001 From: Greg Kurz Date: Wed, 4 Dec 2019 20:43:48 +0100 Subject: ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models The power7_set_irq() and power9_set_irq() functions set this but it is never used actually. Modern Book3s compatible CPUs are only supported by the pnv and spapr machines. They have an interrupt controller, XICS for POWER7/8 and XIVE for POWER9, whose models don't require to track IRQ input states at the CPU level. Drop these lines to avoid confusion. Signed-off-by: Greg Kurz Message-Id: <157548862861.3650476.16622818876928044450.stgit@bahia.lan> Signed-off-by: David Gibson --- target/ppc/cpu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target/ppc') diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e3e8232..f9528fc 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1090,7 +1090,9 @@ struct CPUPPCState { #if !defined(CONFIG_USER_ONLY) /* * This is the IRQ controller, which is implementation dependent - * and only relevant when emulating a complete machine. + * and only relevant when emulating a complete machine. Note that + * this isn't used by recent Book3s compatible CPUs (POWER7 and + * newer). */ uint32_t irq_input_state; void **irq_inputs; -- cgit v1.1