From 0c8d8c8b8fd6db3110a5be3886b1ed9ba89be8b1 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Tue, 19 Jun 2018 10:52:15 +0200 Subject: target/ppc: Add missing opcode for icbt on PPC440 According to PPC440 User Manual PPC440 has multiple opcodes for icbt instruction: one for compatibility with older cores and two 440 specific opcodes one of which is defined in BookE. QEMU only implements two of these, add the missing one. Signed-off-by: BALATON Zoltan Signed-off-by: David Gibson --- target/ppc/translate.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'target/ppc/translate.c') diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5fe1ba6..3a215a1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6707,6 +6707,8 @@ GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE, PPC2_BOOKE206), +GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, + PPC_440_SPEC), GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), -- cgit v1.1