From 03abfd90cfb02aa08f44bbb7141b0aaaf69042ef Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Thu, 19 May 2022 23:59:08 +1000 Subject: target/ppc: Implement lwsync with weaker memory ordering This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync rather than sync. Signed-off-by: Nicholas Piggin Reviewed-by: Richard Henderson Message-Id: <20220519135908.21282-5-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza --- target/ppc/translate.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'target/ppc/translate.c') diff --git a/target/ppc/translate.c b/target/ppc/translate.c index eb42f7e..1d6daa4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4041,8 +4041,13 @@ static void gen_stqcx_(DisasContext *ctx) /* sync */ static void gen_sync(DisasContext *ctx) { + TCGBar bar = TCG_MO_ALL; uint32_t l = (ctx->opcode >> 21) & 3; + if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { + bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; + } + /* * We may need to check for a pending TLB flush. * @@ -4054,7 +4059,8 @@ static void gen_sync(DisasContext *ctx) if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { gen_check_tlb_flush(ctx, true); } - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + + tcg_gen_mb(bar | TCG_BAR_SC); } /* wait */ -- cgit v1.1