From 139d9023f1410591726bbe35908dcfd9d127aad2 Mon Sep 17 00:00:00 2001 From: Nikunj A Dadhania Date: Thu, 27 Apr 2017 10:48:24 +0530 Subject: target/ppc: do not reset reserve_addr in exec_enter In case when atomic operation is not supported, exit_atomic is called and we stop the world and execute the atomic operation. This results in a following call chain: tcg_gen_atomic_cmpxchg_tl() -> gen_helper_exit_atomic() -> HELPER(exit_atomic) -> cpu_loop_exit_atomic() -> EXCP_ATOMIC -> qemu_tcg_cpu_thread_fn() => case EXCP_ATOMIC -> cpu_exec_step_atomic() -> cpu_step_atomic() -> cc->cpu_exec_enter() = ppc_cpu_exec_enter() Sets env->reserve_addr = -1; But by the time it return back, the reservation is erased and the code fails, this continues forever and the lock is never taken. Instead set this in powerpc_excp() Now that ppc_cpu_exec_enter() doesn't have anything meaningful to do, let us get rid of the function. Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/excp_helper.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target/ppc/excp_helper.c') diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index f4ee7aa..a6bcb47 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -728,6 +728,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; + /* Reset the reservation */ + env->reserve_addr = -1; + /* Any interrupt is context synchronizing, check if TCG TLB * needs a delayed flush on ppc64 */ -- cgit v1.1