From a2735cf483814b1c0e5773eee4a52f8e32d438cf Mon Sep 17 00:00:00 2001 From: "Paul A. Clarke" Date: Wed, 18 Sep 2019 09:31:21 -0500 Subject: ppc: Add support for 'mffscrn','mffscrni' instructions ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffscrn' and 'mffscrni' instructions. 'mffscrn' and 'mffscrni' are similar to 'mffsl', except they do not return the status bits (FI, FR, FPRF) and they also set the rounding mode in the FPSCR. On CPUs without support for 'mffscrn'/'mffscrni' (below ISA 3.0), the instructions will execute identically to 'mffs'. Signed-off-by: Paul A. Clarke Message-Id: <1568817081-1345-1-git-send-email-pc@us.ibm.com> Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/dfp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/ppc/dfp_helper.c') diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c index f102177..da8e08a 100644 --- a/target/ppc/dfp_helper.c +++ b/target/ppc/dfp_helper.c @@ -48,7 +48,7 @@ static void dfp_prepare_rounding_mode(decContext *context, uint64_t fpscr) { enum rounding rnd; - switch ((fpscr >> 32) & 0x7) { + switch ((fpscr & FP_DRN) >> FPSCR_DRN0) { case 0: rnd = DEC_ROUND_HALF_EVEN; break; -- cgit v1.1