From 363fd548abd5fbef040ee001c6694672bfb0d798 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 9 Aug 2021 15:45:22 +0200 Subject: ppc: Add a POWER10 DD2 CPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have HAIL but since it does not break the modeling and that we don't plan to support DD1, modify the LPCR mask of all the POWER10 family. Setting the HAIL bit is a requirement to support the scv instruction on PowerNV POWER10 platforms since glibc-2.33. Signed-off-by: Cédric Le Goater Message-Id: <20210809134547.689560-2-clg@kaod.org> Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- target/ppc/cpu_init.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target/ppc/cpu_init.c') diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 319a272..ad7abc6 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -8269,6 +8269,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; + /* DD2 adds an extra HAIL bit */ + pcc->lpcr_mask |= LPCR_HAIL; + pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; pcc->mmu_model = POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) -- cgit v1.1