From 43accc4862e0a88710411b205fdaf833dadf9951 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 1 Jun 2022 18:33:56 -0700 Subject: target/m68k: Implement TRAPV Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson Message-Id: <20220602013401.303699-13-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- target/m68k/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'target/m68k') diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 8b2157c..0dfddaa 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4910,6 +4910,14 @@ DISAS_INSN(trapcc) do_trapcc(s, &c); } +DISAS_INSN(trapv) +{ + DisasCompare c; + + gen_cc_cond(&c, s, 9); /* V set */ + do_trapcc(s, &c); +} + static void gen_load_fcr(DisasContext *s, TCGv res, int reg) { switch (reg) { @@ -6074,6 +6082,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); + INSN(trapv, 4e76, ffff, M68000); INSN(rtr, 4e77, ffff, M68000); BASE(jump, 4e80, ffc0); BASE(jump, 4ec0, ffc0); -- cgit v1.1