From 0ab5953b00b3165877d00cf75de628c51670b550 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 8 Oct 2018 14:55:02 +0100 Subject: target/arm: Handle SVE vector length changes in system mode SVE vector length can change when changing EL, or when writing to one of the ZCR_ELn registers. For correctness, our implementation requires that predicate bits that are inaccessible are never set. Which means noticing length changes and zeroing the appropriate register bits. Tested-by: Laurent Desnogues Signed-off-by: Richard Henderson Message-id: 20181005175350.30752-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target/arm/op_helper.c') diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 952b8d1..430c50a 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1082,6 +1082,7 @@ void HELPER(exception_return)(CPUARMState *env) "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + aarch64_sve_change_el(env, cur_el, new_el); qemu_mutex_lock_iothread(); arm_call_el_change_hook(arm_env_get_cpu(env)); -- cgit v1.1