From d4cc1c21965b3df527cbfbae5a317a9c2ac441e5 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 1 Sep 2021 09:02:39 +0100 Subject: target/arm: Enable MVE in Cortex-M55 We now have a complete MVE emulation, so we can enable it in our Cortex-M55 model by setting the ID registers to match those of a Cortex-M55 with full MVE support. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu_tcg.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'target/arm/cpu_tcg.c') diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ed444bf..33cc75a 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -654,12 +654,9 @@ static void cortex_m55_initfn(Object *obj) cpu->revidr = 0; cpu->pmsav7_dregion = 16; cpu->sau_sregion = 8; - /* - * These are the MVFR* values for the FPU, no MVE configuration; - * we will update them later when we implement MVE - */ + /* These are the MVFR* values for the FPU + full MVE configuration */ cpu->isar.mvfr0 = 0x10110221; - cpu->isar.mvfr1 = 0x12100011; + cpu->isar.mvfr1 = 0x12100211; cpu->isar.mvfr2 = 0x00000040; cpu->isar.id_pfr0 = 0x20000030; cpu->isar.id_pfr1 = 0x00000230; -- cgit v1.1