From 87014c6b3660ce54a57cb72171d6f93306b0c44a Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Thu, 31 Oct 2019 15:27:34 +0100 Subject: target/arm/kvm: host cpu: Add support for sve properties Allow cpu 'host' to enable SVE when it's available, unless the user chooses to disable it with the added 'sve=off' cpu property. Also give the user the ability to select vector lengths with the sve properties. We don't adopt 'max' cpu's other sve property, sve-max-vq, because that property is difficult to use with KVM. That property assumes all vector lengths in the range from 1 up to and including the specified maximum length are supported, but there may be optional lengths not supported by the host in that range. With KVM one must be more specific when enabling vector lengths. Signed-off-by: Andrew Jones Reviewed-by: Eric Auger Reviewed-by: Richard Henderson Tested-by: Masayoshi Mizuma Message-id: 20191031142734.8590-10-drjones@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'target/arm/cpu.h') diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a044d60..e1a66a2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -977,11 +977,13 @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); +void aarch64_add_sve_properties(Object *obj); #else static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n, bool a) { } +static inline void aarch64_add_sve_properties(Object *obj) { } #endif #if !defined(CONFIG_TCG) -- cgit v1.1