From 00e1754ff1f6294a29e08398a120663eac723216 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Tue, 10 Feb 2015 18:12:31 +0000 Subject: target-tricore: fix RRPW_DEXTR using wrong reg RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the other way round. This also fixes that the result of the first shift was not saved in a temp and could overwrite registers that were needed for the second shift. Signed-off-by: Bastian Koppelmann --- target-tricore/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target-tricore/translate.c') diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 989a047..bbcfee9 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -8044,8 +8044,8 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16); } else { temp = tcg_temp_new(); - tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16); - tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16); + tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16); + tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16); tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); tcg_temp_free(temp); } -- cgit v1.1