From ce8536e23f5cc37484f8d56fd81b386f78add542 Mon Sep 17 00:00:00 2001
From: blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Sat, 22 Mar 2008 08:47:14 +0000
Subject:  Convert ldf/ldfsr and stf/stfsr to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4101 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-sparc/translate.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

(limited to 'target-sparc/translate.c')

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index da408e7..e81ef84 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -226,9 +226,7 @@ static void gen_op_store_QT0_fpr(unsigned int dst)
 #ifdef __i386__
 OP_LD_TABLE(std);
 #endif /* __i386__ */
-OP_LD_TABLE(stf);
 OP_LD_TABLE(stdf);
-OP_LD_TABLE(ldf);
 OP_LD_TABLE(lddf);
 #endif
 
@@ -4295,12 +4293,15 @@ static void disas_sparc_insn(DisasContext * dc)
                 switch (xop) {
                 case 0x20:      /* load fpreg */
                     gen_op_check_align_T0_3();
-                    gen_op_ldst(ldf);
-                    gen_op_store_FT0_fpr(rd);
+                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
+                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
+                                   offsetof(CPUState, fpr[rd]));
                     break;
                 case 0x21:      /* load fsr */
                     gen_op_check_align_T0_3();
-                    gen_op_ldst(ldf);
+                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
+                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
+                                   offsetof(CPUState, ft0));
                     tcg_gen_helper_0_0(helper_ldfsr);
                     break;
                 case 0x22:      /* load quad fpreg */
@@ -4422,17 +4423,20 @@ static void disas_sparc_insn(DisasContext * dc)
                 if (gen_trap_ifnofpu(dc))
                     goto jmp_insn;
                 switch (xop) {
-                case 0x24:
+                case 0x24: /* store fpreg */
                     gen_op_check_align_T0_3();
-                    gen_op_load_fpr_FT0(rd);
-                    gen_op_ldst(stf);
+                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+                                   offsetof(CPUState, fpr[rd]));
+                    tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
                     break;
                 case 0x25: /* stfsr, V9 stxfsr */
 #ifdef CONFIG_USER_ONLY
                     gen_op_check_align_T0_3();
 #endif
                     tcg_gen_helper_0_0(helper_stfsr);
-                    gen_op_ldst(stf);
+                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
+                                   offsetof(CPUState, ft0));
+                    tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
                     break;
                 case 0x26:
 #ifdef TARGET_SPARC64
-- 
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