From b350ab758342c764a6ead6ef064b15a72c830808 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 20 Nov 2012 16:15:47 +0100 Subject: target-sh4: Move PVR/PRR/CVR into SuperHCPUClass MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They are never changed once initialized, and moving them to the class will allow to inspect them before instantiating. Signed-off-by: Andreas Färber --- target-sh4/cpu-qom.h | 6 ++++++ target-sh4/cpu.c | 18 +++++++++--------- target-sh4/cpu.h | 3 --- 3 files changed, 15 insertions(+), 12 deletions(-) (limited to 'target-sh4') diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h index 19d8b08..29628c8 100644 --- a/target-sh4/cpu-qom.h +++ b/target-sh4/cpu-qom.h @@ -40,6 +40,9 @@ * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * @name: The name. + * @pvr: Processor Version Register + * @prr: Processor Revision Register + * @cvr: Cache Version Register * * A SuperH CPU model. */ @@ -52,6 +55,9 @@ typedef struct SuperHCPUClass { void (*parent_reset)(CPUState *cpu); const char *name; + uint32_t pvr; + uint32_t prr; + uint32_t cvr; } SuperHCPUClass; /** diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index fba1534..5251aa0 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -156,9 +156,6 @@ static void sh7750r_cpu_initfn(Object *obj) CPUSH4State *env = &cpu->env; env->id = SH_CPU_SH7750R; - env->pvr = 0x00050000; - env->prr = 0x00000100; - env->cvr = 0x00110000; env->features = SH_FEATURE_BCR3_AND_BCR4; } @@ -167,6 +164,9 @@ static void sh7750r_class_init(ObjectClass *oc, void *data) SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); scc->name = "SH7750R"; + scc->pvr = 0x00050000; + scc->prr = 0x00000100; + scc->cvr = 0x00110000; } static const TypeInfo sh7750r_type_info = { @@ -182,9 +182,6 @@ static void sh7751r_cpu_initfn(Object *obj) CPUSH4State *env = &cpu->env; env->id = SH_CPU_SH7751R; - env->pvr = 0x04050005; - env->prr = 0x00000113; - env->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ env->features = SH_FEATURE_BCR3_AND_BCR4; } @@ -193,6 +190,9 @@ static void sh7751r_class_init(ObjectClass *oc, void *data) SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); scc->name = "SH7751R"; + scc->pvr = 0x04050005; + scc->prr = 0x00000113; + scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ } static const TypeInfo sh7751r_type_info = { @@ -208,9 +208,6 @@ static void sh7785_cpu_initfn(Object *obj) CPUSH4State *env = &cpu->env; env->id = SH_CPU_SH7785; - env->pvr = 0x10300700; - env->prr = 0x00000200; - env->cvr = 0x71440211; env->features = SH_FEATURE_SH4A; } @@ -219,6 +216,9 @@ static void sh7785_class_init(ObjectClass *oc, void *data) SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); scc->name = "SH7785"; + scc->pvr = 0x10300700; + scc->prr = 0x00000200; + scc->cvr = 0x71440211; } static const TypeInfo sh7785_type_info = { diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 49dcd9e..f805778 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -179,9 +179,6 @@ typedef struct CPUSH4State { CPU_COMMON int id; /* CPU model */ - uint32_t pvr; /* Processor Version Register */ - uint32_t prr; /* Processor Revision Register */ - uint32_t cvr; /* Cache Version Register */ void *intc_handle; int in_sleep; /* SR_BL ignored during sleep */ -- cgit v1.1