From 702763fa322ea69dde92517735507e0ac3879b5d Mon Sep 17 00:00:00 2001 From: David Gibson Date: Sun, 7 Apr 2013 19:08:20 +0000 Subject: target-ppc: Add more stubs for POWER7 PMU registers In addition to the performance monitor registers found on nearly all 6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an extra control register (MMCRA). This patch adds stub support for them to qemu - the registers won't do anything, but with this change won't cause illegal instruction traps accessing them. They're also registered with their ONE_REG ids, so their value will be kept in sync with KVM where appropriate. Signed-off-by: David Gibson Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target-ppc/cpu.h') diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 99ebf7e..b8b09b9 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1445,6 +1445,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_PERF2 (0x302) #define SPR_RCPU_MI_RBA2 (0x302) #define SPR_MPC_MI_AP (0x302) +#define SPR_MMCRA (0x302) #define SPR_PERF3 (0x303) #define SPR_RCPU_MI_RBA3 (0x303) #define SPR_MPC_MI_EPN (0x303) -- cgit v1.1