From 97ed5ccdee95f0b98bedc601ff979e368583472c Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 17 Aug 2015 17:34:10 +1000 Subject: tlb: Add "ifetch" argument to cpu_mmu_index() This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson --- target-openrisc/cpu.h | 2 +- target-openrisc/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'target-openrisc') diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 36c4f20..560210d 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -403,7 +403,7 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, *flags = (env->flags & D_FLAG); } -static inline int cpu_mmu_index(CPUOpenRISCState *env) +static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) { if (!(env->sr & SR_IME)) { return MMU_NOMMU_IDX; diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index aca1242..473556e 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1653,7 +1653,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, dc->ppc = pc_start; dc->pc = pc_start; dc->flags = cpu->env.cpucfgr; - dc->mem_idx = cpu_mmu_index(&cpu->env); + dc->mem_idx = cpu_mmu_index(&cpu->env, false); dc->synced_flags = dc->tb_flags = tb->flags; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); dc->singlestep_enabled = cs->singlestep_enabled; -- cgit v1.1