From dd5e3b1771b7c528690f2c0714c8e88be07c9bc2 Mon Sep 17 00:00:00 2001 From: aliguori Date: Thu, 29 Jan 2009 17:02:17 +0000 Subject: MTRR support on x86, part 2 (Carl-Daniel Hailfinger) Load and save MTRR state together with machine state. Add support for the MTRRcap MSR which is used by the latest Bochs BIOS and some operating systems. Fix a typo in ext2_feature_name. With this patch, MTRR emulation should be good enough to not trigger any sanity checks in well behaved BIOS/kernel code. Some corner cases for BIOS/firmware usage remain to be implemented, but that can be deferred to another patch. Also, MTRR accesses on hardware not supporting MTRRs should cause #GP. That can be enforced by another patch as well. Signed-off-by: Carl-Daniel Hailfinger Signed-off-by: Anthony Liguori git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6472 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-i386/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'target-i386/cpu.h') diff --git a/target-i386/cpu.h b/target-i386/cpu.h index f1715b2..0a4f1d7 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -251,6 +251,11 @@ #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_MTRRcap 0xfe +#define MSR_MTRRcap_VCNT 8 +#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) +#define MSR_MTRRcap_WC_SUPPORTED (1 << 10) + #define MSR_IA32_SYSENTER_CS 0x174 #define MSR_IA32_SYSENTER_ESP 0x175 #define MSR_IA32_SYSENTER_EIP 0x176 -- cgit v1.1