From 43175fa96add507afee6c0a83ec9ffe0ca130fc3 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 12 Mar 2013 13:16:28 +0100 Subject: target-i386: preserve FPU and MSR state on INIT Most MSRs, plus the FPU, MMX, MXCSR, XMM and YMM registers should not be zeroed on INIT (Table 9-1 in the Intel SDM). Copy them out of CPUX86State and back in, instead of special casing env->pat. The relevant fields are already consecutive except PAT and SMBASE. However: - KVM and Hyper-V MSRs should be reset because they include memory locations written by the hypervisor. These MSRs are moved together at the end of the preserved area. - SVM state can be moved out of the way since it is written by VMRUN. Cc: Andreas Faerber Reviewed-by: Michael S. Tsirkin Signed-off-by: Paolo Bonzini --- target-i386/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'target-i386/cpu.c') diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 79b1bb9..042a48d 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2418,8 +2418,7 @@ static void x86_cpu_reset(CPUState *s) xcc->parent_reset(s); - - memset(env, 0, offsetof(CPUX86State, pat)); + memset(env, 0, offsetof(CPUX86State, cpuid_level)); tlb_flush(s, 1); -- cgit v1.1