From 7ff4d2180b27b3356379ca66738da10ad8b2f73a Mon Sep 17 00:00:00 2001
From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Mon, 7 Feb 2005 12:42:35 +0000
Subject: CF generator for constant operands

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1267 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-arm/op.c        | 5 +++++
 target-arm/translate.c | 3 ++-
 2 files changed, 7 insertions(+), 1 deletion(-)

(limited to 'target-arm')

diff --git a/target-arm/op.c b/target-arm/op.c
index 813c285..5618834 100644
--- a/target-arm/op.c
+++ b/target-arm/op.c
@@ -105,6 +105,11 @@ void OPPROTO op_movl_T1_im(void)
     T1 = PARAM1;
 }
 
+void OPPROTO op_mov_CF_T1(void)
+{
+    env->CF = ((uint32_t)T1) >> 31;
+}
+
 void OPPROTO op_movl_T2_im(void)
 {
     T2 = PARAM1;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e2c5b8f..7223242 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -536,7 +536,8 @@ static void disas_arm_insn(DisasContext *s)
             if (shift)
                 val = (val >> shift) | (val << (32 - shift));
             gen_op_movl_T1_im(val);
-            /* XXX: is CF modified ? */
+            if (logic_cc && shift)
+                gen_op_mov_CF_T1();
         } else {
             /* register */
             rm = (insn) & 0xf;
-- 
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