From 82e14b02a2bd822af6db2ef728a1698b9a24e50c Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 17 Dec 2013 19:42:35 +0000 Subject: target-arm: A64: add support for 1-src RBIT insn This adds support for the C5.6.147 RBIT instruction. Signed-off-by: Alexander Graf [claudio: adapted to new decoder, use bswap64, make RBIT part standalone from the rest of the patch, splitting REV into a separate patch] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/helper-a64.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'target-arm/helper-a64.c') diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index e4c5346..cccaac6 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -49,3 +49,21 @@ uint64_t HELPER(clz64)(uint64_t x) { return clz64(x); } + +uint64_t HELPER(rbit64)(uint64_t x) +{ + /* assign the correct byte position */ + x = bswap64(x); + + /* assign the correct nibble position */ + x = ((x & 0xf0f0f0f0f0f0f0f0ULL) >> 4) + | ((x & 0x0f0f0f0f0f0f0f0fULL) << 4); + + /* assign the correct bit position */ + x = ((x & 0x8888888888888888ULL) >> 3) + | ((x & 0x4444444444444444ULL) >> 1) + | ((x & 0x2222222222222222ULL) << 1) + | ((x & 0x1111111111111111ULL) << 3); + + return x; +} -- cgit v1.1