From b0fe2427511232f361942f672511970e5c75eb4b Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 26 Feb 2014 17:20:03 +0000 Subject: target-arm: Implement AArch64 memory attribute registers Implement the AArch64 memory attribute registers. Since QEMU doesn't model caches it does not need to care about memory attributes at all, and we can simply make these read-as-written. We did not previously implement the AArch32 versions of the MAIR registers, which went unnoticed because of the overbroad TLB_LOCKDOWN reginfo definition; provide them now to keep the 64<->32 register relationship clear. We already provided AMAIR registers for 32 bit as simple RAZ/WI; extend that to provide a 64 bit RAZ/WI AMAIR_EL1. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/cpu.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target-arm/cpu.h') diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 632b4d1..51fa634 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -74,8 +74,10 @@ */ #ifdef HOST_WORDS_BIGENDIAN #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) +#define offsetofhigh32(S, M) offsetof(S, M) #else #define offsetoflow32(S, M) offsetof(S, M) +#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif /* Meanings of the ARMCPU object's two inbound GPIO lines */ @@ -197,6 +199,7 @@ typedef struct CPUARMState { uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ + uint64_t mair_el1; uint32_t c12_vbar; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_context; /* Context ID. */ -- cgit v1.1