From 014406b510faae91b801c8c6fd408a7609f6de0b Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 15 Apr 2014 19:18:45 +0100 Subject: target-arm: Implement AArch64 view of CONTEXTIDR Implement AArch64 view of the CONTEXTIDR register. We tighten up the condition when we flush the TLB on a CONTEXTIDR write to avoid needlessly flushing the TLB every time on a 64 bit system (and also on a 32 bit system using LPAE, as a bonus). Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-arm/cpu.h') diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ec0306b..d0f42fd 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -201,7 +201,7 @@ typedef struct CPUARMState { uint64_t mair_el1; uint64_t c12_vbar; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ - uint32_t c13_context; /* Context ID. */ + uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ uint64_t tpidrro_el0; /* User RO Thread register. */ uint64_t tpidr_el1; /* Privileged Thread register. */ -- cgit v1.1