From 06d76f319f2ea1cf8a66392670a04f649d6280ce Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 20 Jun 2012 11:57:17 +0000 Subject: target-arm: Convert cp15 crn=6 registers Convert the cp15 crn=6 registers to the new scheme. Note that this includes some minor tidyup: drop an unnecessary underdecoding of op2 on OMAPCP cores, and only implement the pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5 cores, which didn't have it. Signed-off-by: Peter Maydell --- target-arm/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'target-arm/cpu.c') diff --git a/target-arm/cpu.c b/target-arm/cpu.c index f8534a7..f37380f 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -251,6 +251,16 @@ static void arm1026_initfn(Object *obj) cpu->reset_fpsid = 0x410110a0; cpu->ctr = 0x1dd20d2; cpu->reset_sctlr = 0x00090078; + { + /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ + ARMCPRegInfo ifar = { + .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), + .resetvalue = 0 + }; + define_one_arm_cp_reg(cpu, &ifar); + } } static void arm1136_r2_initfn(Object *obj) -- cgit v1.1