From f318cec6adcb73c688d68b0874686a30c0f34a2e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 15 Apr 2014 19:18:49 +0100 Subject: target-arm: Implement CBAR for Cortex-A57 The Cortex-A57, like most of the other ARM cores, has a CBAR register which defines the base address of the per-CPU peripherals. However it has a 64-bit view as well as a 32-bit view; expand the QOM reset-cbar property from UINT32 to UINT64 so this can be specified, and implement the 32-bit and 64-bit views of a 64-bit CBAR. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/cpu-qom.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-arm/cpu-qom.h') diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 743985e..82f1bc7 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -148,7 +148,7 @@ typedef struct ARMCPU { * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. */ uint32_t ccsidr[16]; - uint32_t reset_cbar; + uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ -- cgit v1.1