From ad9dcb207b054fa62c7118f6fe4d052e8b26c728 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Fri, 8 Jan 2021 22:42:43 +0000 Subject: gdbstub: drop CPUEnv from gdb_exit() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit gdb_exit() has never needed anything from env and I doubt we are going to start now. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210108224256.2321-8-alex.bennee@linaro.org> --- linux-user/exit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'linux-user') diff --git a/linux-user/exit.c b/linux-user/exit.c index 1594015..70b3440 100644 --- a/linux-user/exit.c +++ b/linux-user/exit.c @@ -34,6 +34,6 @@ void preexit_cleanup(CPUArchState *env, int code) #ifdef CONFIG_GCOV __gcov_dump(); #endif - gdb_exit(env, code); + gdb_exit(code); qemu_plugin_atexit_cb(); } -- cgit v1.1 From 56b5170c87ee3e30221eea7425c2fc4f0cc7d4a3 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 8 Jan 2021 22:42:48 +0000 Subject: semihosting: Move ARM semihosting code to shared directories MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard [AJB: rename arm-compat-semi, select SEMIHOSTING] Signed-off-by: Alex Bennée Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210107170717.2098982-2-keithp@keithp.com> Message-Id: <20210108224256.2321-13-alex.bennee@linaro.org> --- linux-user/arm/meson.build | 3 -- linux-user/arm/semihost.c | 76 ---------------------------------------------- linux-user/meson.build | 1 + linux-user/semihost.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 77 insertions(+), 79 deletions(-) delete mode 100644 linux-user/arm/semihost.c create mode 100644 linux-user/semihost.c (limited to 'linux-user') diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build index 432984b..5a93c92 100644 --- a/linux-user/arm/meson.build +++ b/linux-user/arm/meson.build @@ -1,6 +1,3 @@ -linux_user_ss.add(when: 'TARGET_AARCH64', if_true: files('semihost.c')) -linux_user_ss.add(when: 'TARGET_ARM', if_true: files('semihost.c')) - subdir('nwfpe') syscall_nr_generators += { diff --git a/linux-user/arm/semihost.c b/linux-user/arm/semihost.c deleted file mode 100644 index a1f0f60..0000000 --- a/linux-user/arm/semihost.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * ARM Semihosting Console Support - * - * Copyright (c) 2019 Linaro Ltd - * - * Currently ARM is unique in having support for semihosting support - * in linux-user. So for now we implement the common console API but - * just for arm linux-user. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "hw/semihosting/console.h" -#include "qemu.h" -#include - -int qemu_semihosting_console_outs(CPUArchState *env, target_ulong addr) -{ - int len = target_strlen(addr); - void *s; - if (len < 0){ - qemu_log_mask(LOG_GUEST_ERROR, - "%s: passed inaccessible address " TARGET_FMT_lx, - __func__, addr); - return 0; - } - s = lock_user(VERIFY_READ, addr, (long)(len + 1), 1); - g_assert(s); /* target_strlen has already verified this will work */ - len = write(STDERR_FILENO, s, len); - unlock_user(s, addr, 0); - return len; -} - -void qemu_semihosting_console_outc(CPUArchState *env, target_ulong addr) -{ - char c; - - if (get_user_u8(c, addr)) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: passed inaccessible address " TARGET_FMT_lx, - __func__, addr); - } else { - if (write(STDERR_FILENO, &c, 1) != 1) { - qemu_log_mask(LOG_UNIMP, "%s: unexpected write to stdout failure", - __func__); - } - } -} - -/* - * For linux-user we can safely block. However as we want to return as - * soon as a character is read we need to tweak the termio to disable - * line buffering. We restore the old mode afterwards in case the - * program is expecting more normal behaviour. This is slow but - * nothing using semihosting console reading is expecting to be fast. - */ -target_ulong qemu_semihosting_console_inc(CPUArchState *env) -{ - uint8_t c; - struct termios old_tio, new_tio; - - /* Disable line-buffering and echo */ - tcgetattr(STDIN_FILENO, &old_tio); - new_tio = old_tio; - new_tio.c_lflag &= (~ICANON & ~ECHO); - tcsetattr(STDIN_FILENO, TCSANOW, &new_tio); - - c = getchar(); - - /* restore config */ - tcsetattr(STDIN_FILENO, TCSANOW, &old_tio); - - return (target_ulong) c; -} diff --git a/linux-user/meson.build b/linux-user/meson.build index 2b94e4b..7fe28d6 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -16,6 +16,7 @@ linux_user_ss.add(rt) linux_user_ss.add(when: 'TARGET_HAS_BFLT', if_true: files('flatload.c')) linux_user_ss.add(when: 'TARGET_I386', if_true: files('vm86.c')) +linux_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('semihost.c')) syscall_nr_generators = {} diff --git a/linux-user/semihost.c b/linux-user/semihost.c new file mode 100644 index 0000000..a1f0f60 --- /dev/null +++ b/linux-user/semihost.c @@ -0,0 +1,76 @@ +/* + * ARM Semihosting Console Support + * + * Copyright (c) 2019 Linaro Ltd + * + * Currently ARM is unique in having support for semihosting support + * in linux-user. So for now we implement the common console API but + * just for arm linux-user. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "hw/semihosting/console.h" +#include "qemu.h" +#include + +int qemu_semihosting_console_outs(CPUArchState *env, target_ulong addr) +{ + int len = target_strlen(addr); + void *s; + if (len < 0){ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: passed inaccessible address " TARGET_FMT_lx, + __func__, addr); + return 0; + } + s = lock_user(VERIFY_READ, addr, (long)(len + 1), 1); + g_assert(s); /* target_strlen has already verified this will work */ + len = write(STDERR_FILENO, s, len); + unlock_user(s, addr, 0); + return len; +} + +void qemu_semihosting_console_outc(CPUArchState *env, target_ulong addr) +{ + char c; + + if (get_user_u8(c, addr)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: passed inaccessible address " TARGET_FMT_lx, + __func__, addr); + } else { + if (write(STDERR_FILENO, &c, 1) != 1) { + qemu_log_mask(LOG_UNIMP, "%s: unexpected write to stdout failure", + __func__); + } + } +} + +/* + * For linux-user we can safely block. However as we want to return as + * soon as a character is read we need to tweak the termio to disable + * line buffering. We restore the old mode afterwards in case the + * program is expecting more normal behaviour. This is slow but + * nothing using semihosting console reading is expecting to be fast. + */ +target_ulong qemu_semihosting_console_inc(CPUArchState *env) +{ + uint8_t c; + struct termios old_tio, new_tio; + + /* Disable line-buffering and echo */ + tcgetattr(STDIN_FILENO, &old_tio); + new_tio = old_tio; + new_tio.c_lflag &= (~ICANON & ~ECHO); + tcsetattr(STDIN_FILENO, TCSANOW, &new_tio); + + c = getchar(); + + /* restore config */ + tcsetattr(STDIN_FILENO, TCSANOW, &old_tio); + + return (target_ulong) c; +} -- cgit v1.1 From 0bb446d8b09332e51e6c22a8e36b9ceda2a1bf4d Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 8 Jan 2021 22:42:49 +0000 Subject: semihosting: Change common-semi API to be architecture-independent MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard Signed-off-by: Alex Bennée Reviewed-by: Alistair Francis Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org> --- linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'linux-user') diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fef..42b9c15 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -129,7 +130,7 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_SEMIHOST: - env->xregs[0] = do_arm_semihosting(env); + env->xregs[0] = do_common_semihosting(cs); env->pc += 4; break; case EXCP_YIELD: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 3d272b5..cadfb7f 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "elf.h" #include "cpu_loop-common.h" +#include "hw/semihosting/common-semi.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ @@ -421,7 +422,7 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_SEMIHOST: - env->regs[0] = do_arm_semihosting(env); + env->regs[0] = do_common_semihosting(cs); env->regs[15] += env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: -- cgit v1.1 From a10b9d93ecea0a8f01eb6de56274b1bcb101083b Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 8 Jan 2021 22:42:52 +0000 Subject: riscv: Add semihosting support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard Signed-off-by: Alex Bennée Reviewed-by: Alistair Francis Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org> --- linux-user/qemu.h | 4 +++- linux-user/semihost.c | 8 ++++---- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'linux-user') diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 534753c..17aa992 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -109,6 +109,8 @@ typedef struct TaskState { /* FPA state */ FPA11 fpa; # endif +#endif +#if defined(TARGET_ARM) || defined(TARGET_RISCV) int swi_errno; #endif #if defined(TARGET_I386) && !defined(TARGET_X86_64) @@ -122,7 +124,7 @@ typedef struct TaskState { #ifdef TARGET_M68K abi_ulong tp_value; #endif -#if defined(TARGET_ARM) || defined(TARGET_M68K) +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_RISCV) /* Extra fields for semihosted binaries. */ abi_ulong heap_base; abi_ulong heap_limit; diff --git a/linux-user/semihost.c b/linux-user/semihost.c index a1f0f60..c0015ee 100644 --- a/linux-user/semihost.c +++ b/linux-user/semihost.c @@ -1,11 +1,11 @@ /* - * ARM Semihosting Console Support + * ARM Compatible Semihosting Console Support. * * Copyright (c) 2019 Linaro Ltd * - * Currently ARM is unique in having support for semihosting support - * in linux-user. So for now we implement the common console API but - * just for arm linux-user. + * Currently ARM and RISC-V are unique in having support for + * semihosting support in linux-user. So for now we implement the + * common console API but just for arm and risc-v linux-user. * * SPDX-License-Identifier: GPL-2.0-or-later */ -- cgit v1.1 From 6b80cb25b4165ae2afa525d084366221a2e9b58d Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 8 Jan 2021 22:42:53 +0000 Subject: riscv: Add semihosting support for user mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng Signed-off-by: Alex Bennée Reviewed-by: Keith Packard Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210107170717.2098982-7-keithp@keithp.com> Message-Id: <20210108224256.2321-18-alex.bennee@linaro.org> --- linux-user/riscv/cpu_loop.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'linux-user') diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index aa9e437..9665dab 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -23,6 +23,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "elf.h" +#include "hw/semihosting/common-semi.h" void cpu_loop(CPURISCVState *env) { @@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_SEGV_MAPERR; sigaddr = env->badaddr; break; + case RISCV_EXCP_SEMIHOST: + env->gpr[xA0] = do_common_semihosting(cs); + env->pc += 4; + break; case EXCP_DEBUG: gdbstep: signum = TARGET_SIGTRAP; -- cgit v1.1