From 5a8e01366c5dfe93f608e7d37f385962495d5161 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 19 Aug 2020 21:54:38 -0700 Subject: target/microblaze: Split out FSR from env->sregs Continue eliminating the sregs array in favor of individual members. Does not correct the width of FSR, yet. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson --- linux-user/microblaze/cpu_loop.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'linux-user') diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index c10e3e0..da5e98b 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env) case ESR_EC_FPU: info.si_signo = TARGET_SIGFPE; info.si_errno = 0; - if (env->sregs[SR_FSR] & FSR_IO) { + if (env->fsr & FSR_IO) { info.si_code = TARGET_FPE_FLTINV; } - if (env->sregs[SR_FSR] & FSR_DZ) { + if (env->fsr & FSR_DZ) { info.si_code = TARGET_FPE_FLTDIV; } info._sifields._sigfault._addr = 0; -- cgit v1.1