From dc4d4aaee31cd3ac4020d3b15729f0a104ce8862 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 16 Dec 2020 10:22:32 -0800 Subject: riscv: spike: Remove target macro conditionals Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com --- include/hw/riscv/spike.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include') diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index cddeca2..cdd1a13 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -47,10 +47,4 @@ enum { SPIKE_DRAM }; -#if defined(TARGET_RISCV32) -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64 -#endif - #endif -- cgit v1.1