From d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 25 Sep 2019 16:32:30 +0200 Subject: aspeed/timer: Add support for control register 3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The AST2500 timer has a third control register that is used to implement a set-to-clear feature for the main control register. This models the behaviour expected by the AST2500 while maintaining the same behaviour for the AST2400. The vmstate version is not increased yet because the structure is modified again in the following patches. Based on previous work from Joel Stanley. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 20190925143248.10000-6-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/timer/aspeed_timer.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h index a791fee..1e0288e 100644 --- a/include/hw/timer/aspeed_timer.h +++ b/include/hw/timer/aspeed_timer.h @@ -58,6 +58,7 @@ typedef struct AspeedTimerCtrlState { uint32_t ctrl; uint32_t ctrl2; + uint32_t ctrl3; AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; AspeedSCUState *scu; -- cgit v1.1