From d3765835ed02f91f0c6cbb452874209a6af4a730 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 5 Feb 2019 16:52:37 +0000 Subject: exec: Add target-specific tlb bits to MemTxAttrs These bits can be used to cache target-specific data in cputlb read from the page tables. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20190128223118.5255-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/memattrs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a1642..d4a3477 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,16 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* + * The following are target-specific page-table bits. These are not + * related to actual memory transactions at all. However, this structure + * is part of the tlb_fill interface, cached in the cputlb structure, + * and has unused bits. These fields will be read by target-specific + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. + */ + unsigned int target_tlb_bit0 : 1; + unsigned int target_tlb_bit1 : 1; + unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, -- cgit v1.1