From 018ee7948ff1df9cd98efee6e9d117eadb630cff Mon Sep 17 00:00:00 2001 From: Axel Heider Date: Mon, 31 Oct 2022 00:59:29 +0100 Subject: hw/timer/imx_epit: cleanup CR defines remove unused defines, add needed defines Signed-off-by: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/timer/imx_epit.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index 2acc41e..e2cb962 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -43,7 +43,7 @@ #define CR_OCIEN (1 << 2) #define CR_RLD (1 << 3) #define CR_PRESCALE_SHIFT (4) -#define CR_PRESCALE_MASK (0xfff) +#define CR_PRESCALE_BITS (12) #define CR_SWR (1 << 16) #define CR_IOVW (1 << 17) #define CR_DBGEN (1 << 18) @@ -51,7 +51,7 @@ #define CR_DOZEN (1 << 20) #define CR_STOPEN (1 << 21) #define CR_CLKSRC_SHIFT (24) -#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT) +#define CR_CLKSRC_BITS (2) #define EPIT_TIMER_MAX 0XFFFFFFFFUL -- cgit v1.1 From 1ead962edf1297e223a039167429d4c986bfb90e Mon Sep 17 00:00:00 2001 From: Axel Heider Date: Sat, 19 Nov 2022 15:59:40 +0100 Subject: hw/timer/imx_epit: define SR_OCIF Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/timer/imx_epit.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index e2cb962..783eaf0 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -53,6 +53,8 @@ #define CR_CLKSRC_SHIFT (24) #define CR_CLKSRC_BITS (2) +#define SR_OCIF (1 << 0) + #define EPIT_TIMER_MAX 0XFFFFFFFFUL #define TYPE_IMX_EPIT "imx.epit" -- cgit v1.1 From e662449aa670bff938a011220593dd059b75e84b Mon Sep 17 00:00:00 2001 From: Axel Heider Date: Tue, 25 Oct 2022 12:33:42 +0200 Subject: hw/timer/imx_epit: remove explicit fields cnt and freq The CNT register is a read-only register. There is no need to store it's value, it can be calculated on demand. The calculated frequency is needed temporarily only. Note that this is a migration compatibility break for all boards types that use the EPIT peripheral. Signed-off-by: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/timer/imx_epit.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index 783eaf0..79aff0c 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -74,9 +74,7 @@ struct IMXEPITState { uint32_t sr; uint32_t lr; uint32_t cmp; - uint32_t cnt; - uint32_t freq; qemu_irq irq; }; -- cgit v1.1 From 3d153708943c176befe6712e37b580d4287eba6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 20 Dec 2022 15:25:18 +0100 Subject: hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pointed MouseTransformInfo structure is accessed read-only. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20221220142520.24094-2-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/input/tsc2xxx.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/hw/input/tsc2xxx.h b/include/hw/input/tsc2xxx.h index 5b76ebc..00eca17 100644 --- a/include/hw/input/tsc2xxx.h +++ b/include/hw/input/tsc2xxx.h @@ -30,12 +30,12 @@ uWireSlave *tsc2102_init(qemu_irq pint); uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav); I2SCodec *tsc210x_codec(uWireSlave *chip); uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len); -void tsc210x_set_transform(uWireSlave *chip, MouseTransformInfo *info); +void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info); void tsc210x_key_event(uWireSlave *chip, int key, int down); /* tsc2005.c */ void *tsc2005_init(qemu_irq pintdav); uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len); -void tsc2005_set_transform(void *opaque, MouseTransformInfo *info); +void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info); #endif -- cgit v1.1 From 1e793dd69680a42d3d4ea25450e006322817e0dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 16 Dec 2022 22:49:23 +0100 Subject: hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This function is not used anywhere outside this file, so we can make the function "static void". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-id: 20221216214924.4711-2-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 21e6234..c5683af 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -173,7 +173,4 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); -/* Unmap the range of all the notifiers registered to @mr */ -void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr); - #endif /* HW_ARM_SMMU_COMMON_H */ -- cgit v1.1 From 60c98e72055f6ae944b459a7c0c53962caaba269 Mon Sep 17 00:00:00 2001 From: Jean-Christophe Dubois Date: Tue, 20 Dec 2022 18:27:30 +0100 Subject: i.MX7D: Connect GPT timers to IRQ So far the GPT timers were unable to raise IRQs to the processor. Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 1c5fa6f..50f19d8 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -235,6 +235,11 @@ enum FslIMX7IRQs { FSL_IMX7_USB2_IRQ = 42, FSL_IMX7_USB3_IRQ = 40, + FSL_IMX7_GPT1_IRQ = 55, + FSL_IMX7_GPT2_IRQ = 54, + FSL_IMX7_GPT3_IRQ = 53, + FSL_IMX7_GPT4_IRQ = 52, + FSL_IMX7_WDOG1_IRQ = 78, FSL_IMX7_WDOG2_IRQ = 79, FSL_IMX7_WDOG3_IRQ = 10, -- cgit v1.1 From a1e03956f4fb355d33a8a4d9f23ed35ccbed9ec9 Mon Sep 17 00:00:00 2001 From: Jean-Christophe Dubois Date: Tue, 20 Dec 2022 18:27:43 +0100 Subject: i.MX6UL: Add a specific GPT timer instance for the i.MX6UL The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source. Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/timer/imx_gpt.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h index ff5c8a3..5a1230d 100644 --- a/include/hw/timer/imx_gpt.h +++ b/include/hw/timer/imx_gpt.h @@ -78,6 +78,7 @@ #define TYPE_IMX25_GPT "imx25.gpt" #define TYPE_IMX31_GPT "imx31.gpt" #define TYPE_IMX6_GPT "imx6.gpt" +#define TYPE_IMX6UL_GPT "imx6ul.gpt" #define TYPE_IMX7_GPT "imx7.gpt" #define TYPE_IMX_GPT TYPE_IMX25_GPT -- cgit v1.1 From c73c2798304916a27c21157bbc24acccdeb3c5e2 Mon Sep 17 00:00:00 2001 From: Jean-Christophe Dubois Date: Mon, 26 Dec 2022 11:14:18 +0100 Subject: i.MX7D: Connect IRQs to GPIO devices. IRQs were not associated to the various GPIO devices inside i.MX7D. This patch brings the i.MX7D on par with i.MX6. Signed-off-by: Jean-Christophe Dubois Message-id: 20221226101418.415170-1-jcd@tribudubois.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 50f19d8..4e5e071 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -240,6 +240,21 @@ enum FslIMX7IRQs { FSL_IMX7_GPT3_IRQ = 53, FSL_IMX7_GPT4_IRQ = 52, + FSL_IMX7_GPIO1_LOW_IRQ = 64, + FSL_IMX7_GPIO1_HIGH_IRQ = 65, + FSL_IMX7_GPIO2_LOW_IRQ = 66, + FSL_IMX7_GPIO2_HIGH_IRQ = 67, + FSL_IMX7_GPIO3_LOW_IRQ = 68, + FSL_IMX7_GPIO3_HIGH_IRQ = 69, + FSL_IMX7_GPIO4_LOW_IRQ = 70, + FSL_IMX7_GPIO4_HIGH_IRQ = 71, + FSL_IMX7_GPIO5_LOW_IRQ = 72, + FSL_IMX7_GPIO5_HIGH_IRQ = 73, + FSL_IMX7_GPIO6_LOW_IRQ = 74, + FSL_IMX7_GPIO6_HIGH_IRQ = 75, + FSL_IMX7_GPIO7_LOW_IRQ = 76, + FSL_IMX7_GPIO7_HIGH_IRQ = 77, + FSL_IMX7_WDOG1_IRQ = 78, FSL_IMX7_WDOG2_IRQ = 79, FSL_IMX7_WDOG3_IRQ = 10, -- cgit v1.1